JPS63109677A - Teletext signal processing circuit - Google Patents

Abstract

PURPOSE:To stably detect a state where the continuity of teletext signals cannot be maintained no longer, by producing a gate signal synchronously with a clock out of the clocks for processing teletext signal data and detecting the phase of the gate signal and a synchronizing signal from which a equalizing pulse is removed. CONSTITUTION:An equalizing pulse removing circuit 7 detects the period during which horizontal synchronizing signals exist from data sampling signals (clock) (fsp) and horizontal synchronizing signals (fh) containing equalizing pulses and supplies horizontal synchronizing signals from which equalizing pulses are removed to a horizontal synchronism continuity/discontinuity detecting circuit 9 by using the detecting output. The circuit 9 produces gate signals which are synchronized to the clocks from the data sampling signals (clocks) (fsp). Then the circuit 9 detects the phases of the gate signals and horizontal synchronizing signals (waveform o) from which the equalizing pulses are removed and which are supplied from the equalizing pulse removing circuit 7 and respectively outputs horizontal synchronism continuity/discontinuity detecting signals to output terminal 10 and 10'. Therefore, a state where continuity of teletext signals cannot be maintained no longer can be detected stably.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a teletext signal processing circuit, and particularly to a teletext signal processing circuit that receives a teletext signal superimposed within the vertical blanking period of a television signal, and The present invention relates to a teletext signal processing circuit that processes signals.

(Prior technology) Recently, a new broadcasting service has been teletext broadcasting (hereinafter referred to as
teletext) has been realized.

Furthermore, as a teletext system, there is a coded transmission system (code system) that has better transmission efficiency than the conventional pattern system.

Unlike regular television programs that are organized by time, teletext repeatedly transmits various information and entertainment programs consisting of text, graphics, and additional sounds, allowing viewers to access the information they want when they want it. This is a new broadcasting system that has made it possible to

The above information such as text and images is multiplexed with the television radio waves (video signals) from the broadcasting station currently being broadcast, and the recipient must prepare a receiving device or adapter that can receive teletext. Then, the user can select and enjoy a desired teletext program from among many teletext programs.

In addition, this teletext signal (text signal packet) is transmitted as a digital signal using the vertical blanking period of the current television video signal, and the receiving device decodes the signal and converts it into a television signal. This allows text programs to be viewed by displaying images on the television screen and generating additional sounds such as g-raku.

(Problems to be Solved by the Invention) By the way, in the teletext broadcast using the coded transmission method (code method) described above, the continuity (clock synchronization (CR), Byte synchronization (FC) is guaranteed, and the teletext signal is transmitted from the broadcasting station in such a way that the phase of data across fields of the television signal is not discontinuous.

Therefore, on the receiving side, the i of this transmitted teletext signal is
In order to ensure stable reception by utilizing connectivity,
Various circuit improvements have been made to adapters and receiving devices for receiving teletext broadcasts.

In other words, a data sampling signal @ (clock) is obtained from the color subcarrier frequency of the television signal, and byte synchronization is achieved using a framing code.The data of the teletext signal is further synchronized using this data sampling signal. Digital signal processing is performed by this. Furthermore, the following relationship exists between the data sampling signal frequency (fsp) of this teletext signal, the horizontal scanning frequency (fh) of the television signal (composite video signal 9), and the color subcarrier frequency (fsc). be.

fsp-sha・f sc, f h =, (2/455
)・fsc However, the above continuity cannot be maintained due to synchronized switching by the broadcasting station or various conditions of the broadcasting station (for example, when switching broadcast programs on the same channel or changing the relay location). Therefore, on the receiving side, the broadcasting station performs synchronization switching etc. to stably detect that the continuity of the transmitted teletext signal can no longer be maintained, and as a result, stable reception is possible from now on. It is necessary to be able to do so.

In order to stably detect that the continuity of the teletext signal transmitted as described above can no longer be maintained,
It is necessary to detect the equalization pulse period and to detect a stable horizontal periodic signal that does not include the equalization pulse.

Therefore, in view of the above-mentioned conventional technology, the present invention provides teletext signal processing that stably detects when the continuity of the transmitted teletext signal cannot be maintained due to synchronization switching on the broadcasting station side. The purpose is to provide circuits.

(Means for Solving the Problems) In order to achieve the above object, the present invention receives a teletext signal superimposed within the vertical blanking period of a television signal, and processes the teletext signal by signal processing. a teletext signal processing circuit that obtains a teletext signal data processing clock having a frequency that is a predetermined multiple of the subcarrier frequency of the television signal from a subcarrier of the television signal; and a circuit that obtains an equalization pulse from the television signal. A circuit that separates the synchronization signal containing the @ character number transmission signal, detects the period in which the synchronization signal exists from the data processing clock and the synchronization signal containing the equalization pulse, and uses this detection output to separate the synchronization signal containing the equalization pulse. an equalization pulse removal circuit that removes the equalization pulse from the
A synchronous continuity/discontinuity detection signal is generated by generating a gate signal synchronized with the teletext lock from the teletext signal data processing lock and detecting the phase of this gate signal and the sync signal from which the equalization pulse has been removed. This invention provides a teletext signal processing circuit characterized in that it is equipped with a horizontal synchronization continuity/discontinuity detection circuit that outputs a horizontal synchronization continuity/discontinuity detection circuit.

(Function) In the teletext signal processing circuit configured as described above, a gate signal synchronized with this clock is generated from the teletext signal data processing clock obtained from the subcarrier of the television signal, and is equalized with this gate signal. A synchronous continuous/discontinuous detection signal is output by detecting the phase with the synchronous signal from which the pulse has been removed.

(Embodiment) An embodiment of the teletext signal processing circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a teletext signal processing circuit according to the present invention.

In the figure, an input terminal 1 is supplied with a received television signal (composite video signal) transmitted from a broadcasting station. A character signal (character signal packet) of the encoded transmission method is transmitted during a specific horizontal scanning period within the vertical blanking period of this television signal.

2 is a subcarrier regeneration circuit, 3 is a forward frequency generator, 4 is a phase comparator circuit, and 5 is a voltage controlled oscillator (hereinafter referred to as ■c).

), 6 is a preperiodizer, 7 is an equalization pulse removal circuit, and 8 is an equalization pulse removal circuit.
9 is a synchronous separation circuit, 9 is a horizontal synchronous continuity/discontinuity detection circuit,
10.10' is an output terminal. In addition, the front frequency unit 30 phase comparator circuit 4. The VCO 5° frequency divider 6 constitutes a phase locked loop (PLL).

The subcarrier regeneration circuit 2 converts the frequency tsc[m 3.58 M
The IIZI D1 carrier wave (waveform a in FIG. 2) is reproduced and supplied to the front frequency generator 3. Then, the rXII carrier frequency fsc is frequency-divided to obtain a frequency frequency fsc signal (waveform b in FIG. 2), which is supplied to the phase comparator circuit 4.

The phase comparator circuit 4 has a signal supplied from the pre-frequency divider 3 (waveform b in FIG. 2) and a signal supplied from the pre-frequency divider 6 which divides the output of the VCO 5 (waveform b in FIG. 2). The phase with waveform d) is compared, and if there is a phase difference between them, an error voltage corresponding to the phase difference is generated and supplied to the VCO 5. Then, the VCO 5 draws in a signal of a new phase using this error voltage and outputs it. Furthermore, the signal output from this VCO 5 (waveform C in FIG. 2 (waveform C' in FIG. 4)
)) is supplied to the equalization pulse removal circuit 7 and the horizontal synchronization continuity/discontinuity detection circuit 9 as a data sampling signal (clock) with a frequency fsp[=5.7 MIIzl.

Further, the equalization pulse removal circuit 7 is supplied with a horizontal synchronization signal (with a waveform obtained by inverting the waveform e in FIG. 4) having a frequency fh[-15.7ktlzl] separated by a synchronization separation circuit 8. Note that this horizontal synchronization signal includes an equalization pulse.

The equalization pulse removal circuit 7 detects the period in which the horizontal synchronization signal exists from the data sampling signal (clock) (fsp) and the horizontal synchronization signal (fh) including the equalization pulse, and uses this detection output to detect the period in which the horizontal synchronization signal is present, including the equalization pulse. The equalization pulse is removed from the horizontal synchronization signal, and the horizontal synchronization signal from which the equalization pulse has been removed is supplied to the horizontal synchronization continuity/discontinuity detection circuit 9.

The horizontal synchronization continuity/discontinuity detection circuit 9 generates a gate signal synchronized with this clock from the data sampling signal (ri, lock) (fsp), and uses this gate signal and the equalization pulse supplied from the equalization pulse removal circuit 7. Continuous horizontal synchronization by detecting the phase with the horizontal synchronization signal (waveform 0) from which pulses have been removed
The discontinuous detection signals are output to output terminals 10 and 10', respectively.

FIG. 3 is a diagram showing a specific circuit of the equalization pulse removal circuit 7 constituting the circuit of the present invention.

In the same figure, terminals 20 and 21 are connected to data sampling signals (waveform C in FIG. 2 (waveform C in FIG.
Waveform C' in the figure
>(rh) is supplied.

The data sampling signal (
fsp) is supplied to the clock terminal of the counter 22, and is also supplied to the clock terminals of the counter 23 and counter 24. Further, the horizontal synchronizing signal (fh) containing the snow conversion pulse supplied via the terminal 21 is inverted via the inverter 25 to form the waveform e in FIG. 4, and the D flip 7
It is supplied to the clock terminal of 0/2G. Here, the fifth
The waveform e' in the figure is shown by changing the time axis of the waveform e in FIG. 4, and one pulse of the waveform e' in FIG. 5 corresponds to the waveform e in FIG.

The D flip-flop 26 is triggered on the rising edge of the waveform e(e') applied to the output terminal;
Waveform f supplied from the output of the NAND circuit 27, which will be described later.
reset by . And flip flop 2
The output of 6 is supplied to the D terminal of this D flip-flop 26 and the reset terminal R of the counter 22.

When the D flip-flop 26 is triggered, the output of the D flip flop 26 becomes 'L'°, which enables the counter 22 to count. And counter 22
starts counting the data sampling signal (fsp) of waveform C1C' supplied to the clock terminal.

C, D, E output terminals of counter 22 (i.e., 23.
A NAND circuit 27 is connected to the output terminal (24, 25 output terminal), and when the counter 22 detects a predetermined count value (“28” in this connection), the NAND circuit 27
A detection signal (waveform f in FIG. 4) is output from the D-flip 70, and this is supplied to the reset terminal R of the D-flip 70 knob 2G. Therefore, the output of the D flip flop 70 knob 26 is "L" during a period corresponding to 28 clock cycles, and the output of the D flip flop 26 has a pulse width (approximately 49 μsec) that is approximately equal to the horizontal synchronizing signal. A signal (waveforms a and a' in FIGS. 4 and 5) is obtained.

Here, waveform q' in FIG. 5 is shown by changing the time axis of waveform 9 in FIG. 4, similar to the relationship between waveform e and waveform e' described above. One pulse of waveform 9' corresponds to waveform q in FIG.

Further, the D terminal of the D flip-flop 70 tube 28 is supplied with the power supply Vcc, which is a signal of "Hp+," and the clock terminal thereof is supplied with the waveform G (Q'
) is supplied. And this D flip-flop 28
is triggered by the waveform Q(g') and reset by the waveform i output from the NAND circuit 31, which will be described later, and its output (waveform h in FIG. 5) is the D of the D flip 70 knob 29.
'Supplied to 4 children.

Furthermore, the output of the D flip-flop 28 is output to the counter 23.
while being supplied to the clock terminal of the D flip 70 tube 30.

Further, the D flip-flop 29 is triggered by the waveform Q(g') and reset by the waveform j output from the NAND circuit 32, which will be described later, and its output is output from the D flip 70 knob 3.
0 D[supplied to child; Furthermore, D flip-flop 2
The output of 9 is supplied to the reset terminal R of the counter 24.

In this way, the D flip-flops 28 and 29 are connected in a conventional manner, so when the D flip-flop 28 is in the set state (H"), the D flip-flops 28 and 29 are connected in a clock (waveform Q, Q ”) will not be set unless input.

The counter 23 counts the data sampling signals (waveforms c, c') supplied to its clock terminal only when the D flip-flop 28 is in the set state, and counts the data sampling signals (waveforms c, c') supplied to its E, F, G, H output terminals (i.e., 25.26.2)
, 28 output terminals) detects a predetermined count value, and outputs a detection signal (waveform i in FIG. 5) from this NAND circuit 31. Then, until the D flip-flop 28 is reset by this detection signal, the counter 23 continues to count the data sampling signals (waveforms c, c') supplied to the clock terminal.
.

Continue to play.

Here, the predetermined count value detected by the NAND circuit 31 described above is set to a clock count time corresponding to a period greater than th/2 (where th is the horizontal synchronization signal I!l]) and smaller than th. In this connection, the counter value is 3th/4: "240"), and the D flip-flop 29 is not set during the period when there is no equalization pulse. .

Therefore, during the equalization pulse period, after the D flip-flop 28 is set, the clock (waveforms Q, Q') is input to its clock terminal th/2 later, and at this time, the D flip-flop 28 is in the set state. Since it is in
The D flip 70 knob 29 is set.

On the other hand, the D flip-flop 29. The counter 24 and the NAND circuit 32 are connected to the D flip-flop 28 described above.
．． It has the same configuration as the counter 23 and the NAND circuit 31, and its operation is also the same.

That is, the counter 24 counts the data sampling signal (waveform C1c') supplied to its clock terminal only when the D flip-flop 29 is in the set state, and counts the data sampling signal (waveform C1c') supplied to its E, F, G, 'H output terminal (i.e. , 25
．． A predetermined count value is detected by a NAND circuit 32 connected to the output terminals 2B, 2), and 2B output terminals), and a detected signal (waveform j in FIG. 5) is output from this NAND circuit 32. Then, by this detection signal, the D flip-flop 29
Until the counter 24 is reset, the counter 24 receives the data sampling signals (waveforms c, c'
) continues counting.

Here, the predetermined count value detected by the NANO circuit 32 described above is set to th/2 (however, t
Set (connect as above) so that the clock count time corresponds to a period larger than h (horizontal synchronization signal period) and smaller than th (in this connection, the counter value is 3th/4: "240 ”').

Therefore, the ζ output of the D flip-flop 29 has a pulse train (
Waveform k) is generated.

The ζ output (waveform k) of this D flip-flop 29 is supplied to the DI terminal of the D flip-flop 30, and the ζ output (inverted waveform of the waveform) of the D flip-flop 28 is supplied to the clock terminal of this D flip-flop 30. be done. And the D flip-flop 30 is the D flip-flop 28
The equalization pulse period detection signal (waveform 1) in which only the equalization pulse period is "T1" is obtained as the ζ output.

Also, N
The ANO circuit 33 is connected, and the count value of the counter 23 is set so that this NAND circuit 33 detects a clock count value corresponding to a period exceeding "O (zero)" and smaller than th/2. (In the case of this connection, the count value is th/4: "80").

The output (waveform m) of the NAND circuit 33 is output to the gate circuit 35.
．． The output of the NAND circuit 31 (waveform i) is supplied to the set terminal S of the RS flip-flop 34.

The output terminal of the RS flip-flop 34 outputs a gate signal (waveform n) in which the period of the horizontal synchronizing pulse is '1.1' and the period of the equalization pulse is '1.1'.

By supplying this gate signal (waveform n) and the output of the D flip 70 tube 2G (waveforms Q, Q') to the AND circuit 37, the output terminal of the AND circuit 37 outputs a horizontal synchronization pulse from which the equalization pulse has been removed. A signal @ (waveform 0) is obtained, which is output via terminal 38.

As described above, the ζ output terminal of the D flip-flop 30 receives the equalization pulse period detection signal @ (waveform l) in which only the equalization pulse period is H", and the output terminal of the AND circuit 37 outputs the equalization pulse period detection signal @ (waveform l). A horizontal periodic signal (waveform 0) with pulses removed is obtained.

FIG. 6 is a diagram showing a specific circuit of the horizontal interval m continuity/discontinuity detection circuit 9, which is a main part of the circuit of the present invention.

In the same section, data sampling signals (waveform C in FIG. 2) output from the VCO 5 and equalization pulse removal circuit 7 in FIG.
(waveform C' in FIG. 4)) (f 3p) and a horizontal synchronizing signal (waveform 0 in FIG. 5) with the equalization pulse removed.

The data ringing signal supplied via terminal 40 (
f sp) is supplied to a 1/364 frequency divider 42, where the frequency is divided by 1/364 and supplied to a gate signal generation circuit 43. Then, the gate signal generation circuit 43 generates a gate signal (waveform p in FIG. 7) synchronized with this data sampling signal from the supplied data sampling signal frequency-divided by 1/364, and this generates a gate signal (waveform p in FIG. 7) that is transmitted to the shift register 44. S
i Supplied to GW child.

This gate signal, as shown by waveform p in FIG. 7, corresponds to the rising edge (leading edge) of the horizontal synchronization signal @ (waveform e) of the data 9 sampling pulses of waveform C' in FIG. 1 from the 179th pulse with the pulse as the 1st pulse
This signal is “He+” for a period up to the 85th pulse, and the period of this gate signal is 1/(364 fsp).

Further, the horizontal synchronizing signal (waveform 0) from which the equalization pulse has been removed is supplied via the terminal 41 and is supplied to the clock terminal of the shift register 44 .

Each 8-bit output of the shift register 44 is connected to an AND circuit 45 and an inverted AND circuit (i.e., the shift register 4
4, which inverts the output of 4 and performs an AND gate. The output of the AND circuit 45 is then supplied to the clock terminal of the D flip-flop 47, and
The output of the inverting AND circuit 4G is supplied to the clock terminal of the D flip-flop 48. D flip-flop47.
The power supply Vcc, which is an "H" signal, is supplied to the Di terminal 48.

The Q output of the D flip-flop 47 outputs a continuous detection signal (“H”) via the terminal 49, and the output of the D flip-flop 47 is supplied to the reset terminal R of the D flip-flop 48.

Further, the Q output of the D flip-flop 48 outputs a discontinuity detection signal (“H”) via the terminal 50, and the O output of the D flip-flop 48 is supplied to the reset terminal R of the D flip-flop 47.

Now, in a continuous state where the phase of the horizontal synchronizing signal (waveform 0) supplied from the terminal 41 is continuous, as shown in FIG. 7, the leveler II]t='<waveform. ) is in the gate signal (H period of waveform p). At this time, each of the 8-bit outputs of the shift register 44 receives an "H" output as t, and the D flip-flop 47 outputs "H". The Q output becomes H'' (waveform Q+ in FIG. 7), and this is outputted from the terminal 49 as a continuous detection signal. In addition, at this time, D flip 7
The Q output of the 0 knob 48 is "L" (waveform q1' in Fig. 7).
)become.

On the other hand, when the broadcasting station performs synchronization switching and the phase of the horizontal synchronizing signal (waveform 0') becomes discontinuous (i.e., discontinuous), the horizontal synchronizing signal (waveform 0') is the gate signal (waveform p
It falls outside of the period of “(1”). At this time, each 8-bit output of the shift register 44 obtains 8 degrees of LII, and the Q output of the D flip-flop 48 becomes 1"" (waveform q2' in FIG. 7), which is an error. It is output from the terminal 50 as a continuous detection signal. At this time, the Q output of the D flip 70 knob 47 is L" (waveform q2 in FIG. 7).
become.

As described above, in a continuous state where the phase of the horizontal synchronization signal @ (waveform 0) is continuous, a continuous detection signal (゛tobi) is obtained at the Q output (terminal 49) of the D flip-flop 47, and on the other hand, The broadcasting station side performs synchronization switching, etc., and horizontal open f.
The phase of the ill signal (waveform 0') becomes discontinuous fi
(that is, a discontinuous state), the Q output (terminal 50) of the D flip-flop 48 receives a discontinuity detection signal (“H”).
) is obtained.

In this way, it is possible to stably detect that the 21 continuity of the teletext signal transmitted from the broadcasting station can no longer be maintained. Further, this detection signal can be supplied to, for example, a teletext receiving device or an adapter control device (signal processing control microcomputer) to perform signal processing control corresponding to this discontinuous state.

(Effects of the Invention) As described above, according to the teletext signal processing circuit of the present invention, a gate signal synchronized with the teletext signal data processing clock is generated, and the gate signal and the equalization pulse are removed. It outputs a synchronization continuity/discontinuity detection signal by detecting the phase with the synchronization signal, so it can stably detect when the broadcasting station performs synchronization switching and can no longer maintain the continuity of the teletext signal being transmitted. It has the feature of being able to be detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a teletext signal processing circuit according to the present invention, and FIGS. 2 and 4. 5 and 7 are signal waveform diagrams of various parts of the circuit of the present invention, FIG. 3 is a diagram showing a specific circuit of the equalizing pulse removal circuit 7 constituting the circuit of the present invention, and FIG. 6 is a diagram of the circuit of the present invention. This figure shows the specific circuit of the horizontal open continuity/discontinuity detection circuit 9, which is the main part. 1... Input terminal, 2... Subcarrier regeneration circuit, 3...
- Tongue frequency generator, 4... Phase comparator circuit, 5... Voltage controlled oscillator (VCO), 6... Front frequency generator, 7... Equalization pulse removal circuit, 8... Synchronous separation Circuit, 9... Horizontal synchronization continuity/discontinuity detection circuit, 10, 10'... Output terminal, 20, 21.38.40.41.49.50... Terminal, 22, 23.24...・Counter, 25...Inverter, 2G, 28.29.30.47.48...D
Flip-flop, 27, 31.32.33...NA
NDAND circuit...RS flip-flop, 35.3
()...Gate circuit, 37, 45...AND circuit,
42... 1/364 frequency divider, 43... Gate signal generation circuit, 44... Shift register, 46... Inversion A
ND circuit. Le 1 Father 6 Mountain

Claims (3)

[Claims] (1) A teletext signal processing circuit that receives a teletext signal superimposed within a vertical blanking period of a television signal and processes the teletext signal, the circuit comprising: a subcarrier of the television signal; a circuit for obtaining a teletext signal data processing clock having a frequency that is a predetermined multiple of the subcarrier frequency; a circuit for separating a synchronization signal including an equalization pulse from the television signal; the teletext signal data processing clock; an equalization pulse removal circuit that detects a period in which a synchronization signal exists from a synchronization signal that includes an equalization pulse, and removes the equalization pulse from the synchronization signal that includes the equalization pulse based on the detection output; and the teletext signal data processing. A horizontal synchronization continuous/discontinuous detection signal is generated by generating a gate signal synchronized with this clock from an ordinary clock, and outputting a synchronization continuity/discontinuity detection signal by detecting the phase of this gate signal and a synchronization signal from which the equalization pulse has been removed. A teletext signal processing circuit comprising a continuous detection circuit. (2) The teletext signal processing circuit according to claim 1, wherein the circuit for obtaining the clock for teletext signal data processing is constituted by a phase-locked loop circuit. (3) The horizontal synchronization continuity/discontinuity detection circuit includes a frequency divider that divides the teletext signal data processing clock into a synchronization signal frequency, and synchronization with the teletext signal data processing clock from the output of this frequency divider. a gate signal generation circuit that generates a gate signal, and a gate signal generation circuit that receives the gate signal as data and clocks it with a synchronization signal from which the equalization pulse has been removed, and detects the phase of the gate signal and the synchronization signal from which the equalization pulse has been removed. A teletext broadcast according to claim 1, comprising a shift register and a detection circuit that detects synchronous continuity/discontinuity from the output of the shift register and outputs a synchronous continuity/discontinuity detection signal. signal processing circuit.