GB2122450A - Line deflection circuit for a picture display device - Google Patents

Abstract

A line synchronizing circuit for a picture display device, comprising a regenerator (1,7) which during operation derives from the incoming first line synchronizing signal (a) a second line synchronizing signal (c) to be applied to a line phase control loop (8,9,10,11,12). The regenerator comprises a delay element (1), for example a shift register, which delays the signal applied to it in its totality, and which has an inverting output (b) and a processing stage which is provided by, for example, an AND-gate (7). The delay provided by the delay element (1) is approximately equal to or shorter than half the anticipated duration of an incoming line synchronizing pulse. Provides corresponding line pulses (d) during the field trace and field blanking intervals. <IMAGE>

Description

SPECIFICATION Line synchronizing circuit for a picture display device The invention relates two a line synchronizing circuit for a picture display device, comprising means for applying a composite (first) synchronizing signal contained in an incoming video signal to a regenerator for generating in operation and during the field trace period a second synchronizing signal for application to a line phase control loop for generating a signal of line frequency which has a substantially fixed phase relation with the line synchronizing signal present in the second synchronizing signal, the second synchronizing containing pulses ofthe linefrequencywhich has substantially constant duration and whose lead- ing edges have a substantially fixed phase position relative to the leading edges ofthe pulses in the first synchronizing signal,the regenerator comprising a delay elementfor delaying the first synchronizing signal, and a processing stage having a first input to which thefirstsynchronizing signal is applied and a second inputto which the delayed signal is applied.

Such a line synchronizing circuit is disclosed in United States Patent No. 3 530 238. This prior art circuit also comprises a clock generator generating a clock signal of twice the line frequency which is delayed bythe same duration asthefirstsynchronizing signal. These two delayed signals and also the first synchronizing signal are applied to the processing stage provided by an AND-gate, at the output of which the regenerated, second synchronizing signal is present. This comprises pulses of the line frequency whose duration is substantially constant and which occur during the second half of the original line synchronizing pulses. So the leading edges thereof occur at predetermined instants which succeed each otherwith the line period interval.

The prior art circuit has the advantage that the content ofthe output signal of a phase discriminator which is part of the line phase control loop remains constant in the synchronised state ofthe loop. During thetwo equalising periods in the field blanking period the regenerated signal does not however contain a pulse. This results in a deviation ofthe content ofthe said output signal relative to the target value thereof and, consequently, in an error in the control which has not yet been eliminated at the end ofthefield blanking period. As a result thereof the first lines ofthe field have an incorrect phase due to which vertical straight lines atthetop ofthe picture display screen will be displayed as curved lines.

The invention has for its object two provide a circuit of the above-described type which is improved in the above respect.

The invention provides a line synchronizing circuit of the type described in the opening paragraph which is characterised in that the delay produced by the delay element is substantially equal to orshorterthan halfthe anticipated duration of a line synchronizing pulse present in the first synchronizing signal and that the regenerator also comprises an inverting stage for inverting one ofthe signals applied to the processing stage, the second synchronizing signal containing in operation and also during the field blanking period, pulses ofthe said substantially constant duration and whose leading edges have the said same substantially fixed phase relationship.

Preferably, the delay element is of a type which causes substantially no change in the shape ofthe signal applied to it. This increases the insensitivity to noise considerably.

If the line phase control circuit comprises an oscillator for generating in the nominal state a signal whose frequency is a multiple of the line frequency, then the delay element may be a shift registerfor which the signal from the oscillator is the clock signal.

If the means for applying the first synchronizing signal to the regenerator comprises a sync. separator whose output signal can only assume two values then the processing stage may be a coincidence stage.

The invention will now befurtherdescribed byway of example with reference to the accompanying drawing, in which: Figure 1 shows a first embodiment of a regenerator which may be used with the present invention, Figure 2 shows waveforms occurring therein, Figure 3 shows a basic circuit diagram of a line synchronizing circuit according to the invention with a second embodiment of a regenerator, and Figure 4 shows waveforms occurring during the field blanking period in both embodiments.

In Figure 1 ,the regenerator is in the form of a differentiating filter, followed by a rectifier. The synchronizing signal received from a sync. separator is applied thereto. A known, simple differentiating filter is provided by a high-pass filter, with which the leading edge of an incoming pulse can be derived whilethe pulse produced in response to the trailing edge is removed by means ofthe rectifier. Such a filter has however the drawback that the higherfrequencies are less attenuated therefrom than the lowerfrequencies. As the frequency spectrum ofthe line synchroinizing signal contains the greater part of its information in the lowerfrequencies,this implies that the noise behaviourwill be poor.

The filter shown in Figure 1 comprises a delay element 1, by which the synchronizing signal is delayed. Element 1 is of a type, for example a delay line which delays the signal applied to it in its totality, without any appreciable change of its shape. The resultant, delayed signal is thereafter inverted by means of an inverter stage 2. The output sinal of stage 2 and also the non-delayed synchronizing signal are applied to an adder stage 3. In Figure 2a two positively-going line synchronizing pulses H are shown which are present at the input ofthe filter.

Figure 2b shows the signal obtained at the output of stage2.The'ivholeinputsignaland notonlythe leading edges thereof are delayed by a predetermined time. The signal obtained by addition in the adder stage is shown in Figure 2c. The positive portion thereof (Figure 2d) is applied to a line phase control loop via rectifier 4. From the time diagrams of Figure 2, in which Tdesignatesthe line period, i.e. approximately 64 us for the European or American standards, it appearsthatthe leading edges of the regenerated pulses coincide with those ofthe input signal, while the trailing edges occur after a constant period oftime, which is equal to the delay produced by element 1.A delaywhich is not longerthan the duration ofthe shortest pulses which may be present in the incoming signal, more specifically the equalising pulse, i.e. half the duration of a line synchronizing pulse, or approx imately2.4 us is chosen as the delay. There is a certain degree offreedom forthe choice ofthe delay, it will be obviousfora person skilled in the artthattoo short a duration increases the sensitivity to noise of the circuit.

In Figure 2a an arrow denotes a brief noise pulse N.

From Figures 2b, cand dit can be seen that pulse N is conveyed by the circuit without deterioration ofthe desired signal. If element 1 were formed by monostable multivibrators which are elements responding to edges, then in Figure 2d a pulse having a not inconsiderable duration which might have a detrimental effect on the line phase control loop would occur instead of a brief noise pulse. In addition, if the delaywereto vary, for example due to temperature effects, then the time positions ofthe edges ofthe delay pulseswould vary. In contrast therewith the leading edges ofthe pulses in Figure 2d do not vary in this case.The signal available after rectifier4 is consequently in the form of pulses of the line frequency having a shorter duration than the original pulses H, the noise sensitivity being slightly poorer, butthe sensitivity to disturbance pulses not having deteriorated.

Figure 3 shows a possible embodiment of a line synchronizing circuit in which a variant ofthe circuit of Figure 1 is used. Herein reference numeral 5 denotes a low-passfiltertowhich an incoming video signal is applied, which is generated and processed in,for example, the receiving portion of a television receiver.

Filter5 has a bandwidth of approximately 1 MHzand slightly attenuates the noise. The signal is thereafter applied to a sync separator 6, which produces a composite synchronizing signal. If separator 6 is of such a, known, construction that its output signal can only assumetwo values, then the generator may be of the construction shown in Figure 3. The signal from separator6 is applied to a field synchronizing separator not shown, for use in a field synchronizing circuit, to delay element 1 having an inverted output and to an AND-gate 7. The delay is approximately equal to half the prescribed duration of a line synchronizing pulse.

Gate 7 operates as a coincidence stage and a rectifier is not required. Atthe output of gate 7 a regenerated synchronizing signal is available in which the pulses are of a shorter duration than the incoming pulses, while the leading edges coincide with those ofthe incoming signal.

The line phase control loop to which the signal from gate 7 is applied comprises, in succession, a phase discriminator 8, a loopfilter9 and a voltage-controlled oscillator 10. Oscillator 10 has a nominal frequency of 40 MHz. The signal from this oscillator is divided by 2560 by means of a frequency divider circuit 11. So in the nominal state of the loop, circuit 11 generates a signal having a frequency of 15.625 kHz, i.e. the line frequency (European standard),which is applied to a control pulse circuit 12. Circuit 12 generates a number ofsignalsofthe linefrequencyfordifferent portions of the picture display device of which the circuit shown in Figure 3forms part, inter alia the control signal for the line (horizontal) deflection.In a different, known, manner a second line phase control loop can be inserted between circuit 12 and the line deflection circuit. One of the signals produced by circuit 12 is applied to phase discriminator8in which the phases ofthis signal is compared with that of the line synchronizing pulses at the output of gate7, as a result ofwhich a control voltage for oscillator 10 is generated.The control loop of Figure 3 may also comprise a concidence detectorforchanging the loop gain in known manner between the pulled-in and the non pulled-instate and/or on reception of a signal generated by a video pick-up and display arrangement and for switching-on and off, also in known manner, a gate circuit by means ofwhich the signal applied by circuit 12to discrimiator8 is keyed.

The signal generated by oscillator 10 is used as a clock signal in different portions ofthe picture display device. Delay element 1 is provided by a 94-bit shift register and the said clock signal is also applied to it.

So it produces a delay of 94 periods of the clock signal, i.e. approximately halfthe prescribed duration of the line synchronizing pulses.

During thefield trace period phase discriminator 8 receives the regenerated synchronizing signal shown in Figure 2d, either from rectifier 4, or from gate 7, and also the signal of the line frequency from circuit 12.

Figure 4a shows a portion ofthe signal applied to element 1 during the field blanking period. This signal comprises equalising pulses E which are of the same sense as the line synchronizing pulses but whose duration is half the duration of these pulses and whose repetition rate is twice the line frequency. After having been delayed by approximately the duration of a pulse E, and after having been inverted the pulses of Figure 4b are obtained. Figure 4c illustrates the signal at the output ofthe regenerator. The pulses in this signal have approximatelythe same duration as pulses E.

Figure4d illustratesthe signal applied by circuit 12to discriminator8. It is a signal which is keyed atthe line frequency, and an edge of which substantially coincides in the synchronized state ofthe control loop formed by element 8to 12 with the centre of a pulse shown in Figure 4c and consequently has a constant, very small phase, difference with respecttothe pulses shown in Figure 4a, while the pulse of Figure 4cwhich occurs in the meantime between pulses shown in Figu re 4d does not affect the control.

During the field synchronizing interval the signal shown in Figure 4a contains field serration pulses S, which have the same duration as line synchronizing pulses but are ofthe opposite sense and whose repetition rate is twice the line frequency. From Figure 4 is will be apparent that in the said interval the regenerated signal of Figure 4c comprises pulses having the same duration and the same time position relative to the signal of Figure 4d as in the remaining period oftime. From the Figure it will also be apparent that the leading edge ofthefield synchronizing pulse Vprecedingthefirstfieldserration pulse S produces a pulseatthe output of element4 or element7, respectively, which has the same duration and the same time position. So the pulses ofthe regenerated line synchronisation signal have approximatelythe same duration and also the correcttime position during the entire field period. Since no disturbance of the line synchronizing circuit is caused during the field blanking period, the bandwidth of the control loop can be reduced, which improves its noise behaviour and at least compensates for the above-mentioned, slight deterioration caused bythere generator.

It will be obvious that the regenerator may be of a different construction than shown in Figures 1 and 3, as regards, for example, the place of the inverter stage orthe conductivity direction ofthe rectifier. It will also be obvious that the delay element may be implemented in any known manner, for example using analog techniques.

Claims (7)

1. A line synchronizing circuit for a picture display device, comprising meansforapplying a composite (first) synchronizing signal contained in an incoming video signal to a regeneratorfor generating in operation and during the field trace period a second synchronizing signal for application to a line phase control loopforgenerating a signal of linefrequency which has a substantially fixed position relation with the line synchronizing signal present in the second synchronizing signal, the second synchronizing signal containing pulses of line frequency which have a substantiallyconstantduration and whose leading edges have a substantially fixed phase relation with the leading edges ofthe pulses in the first synchronizing signal, the regenerator comprising a delay elementfor delaying the first synchronizing signal, and a processing stage having a first inputto which the first synchronizing signal is applied and a second input to which the delayed signal is applied, characterised in that the delay produced by the delay element is substantially equal to or shorter than half the anticipated duration of a line synchronizing pulse present in the first synchronizing signal and that the regerator also comprises an inverting stage for inverting one of the signals applied to the processing stage, the second synchronizing signal containing in operation and also during the field blanking period, pulses of the said substantially constant duration and whose leading edgeshavethesaidsamesubstantiallyfixed phase relationship.

2. A circuit as claimed in Claim 1, characterised in thatthe delay element is of a type which causes substantially no change in the shape ofthe signal applied to it.

3. A circuit as claimed in Claim 2, the line phase control loop comprising an oscillatorfor generating in the nominal state a signal whose frequency is a multiple of the line frequency, characterised in thatthe delayelementis a shift registerforwhich thesignal from the oscillator is the clock signal.

4. A circuit as claimed in Claim 1 or 2, characte- rised in that the leading edges ofthe pulses in the second synchronizing signal coincide with the leading edges ofthe pulses in the first synchronizing signal.

5. A circuit as claimed in Claim 4, characterised in thatthe processing stagecomprisesan adder stage for adding togetherthe signals applied to the processing stage and a rectfierfor passing signal components ofthe obtained signal whose polarity corres ponds to the polarity ofthe pulses in the first synchronizing signal.

6. Acircuitasclaimed in Claim 4, characterised in that the means for applying the first synchronizing signal to the regenerator comprise a sync. separator whose output signal can only assume two values, characterised is that the processing stage is a coincidence stage.

7. A line synchronizing circuit substantially as herein described with reference to the accompanying drawings.