JPS63108596A - Read only memory device - Google Patents

Abstract

PURPOSE:To reduce the consumption of power and to execute a reading by constituting a current supply transistor means of a pair of transistors for crossing and connecting a drain and a gate mutually and turning off when the drain goes to a first reference voltage. CONSTITUTION:A pair of PMOS transistors (TR) Q1, Q2 of which a source is connected to a source potential and NMOSTRQ11-Q1N of which a gate is connected respectively to input terminals 1-N are provided. The drains of the TRs Q1, Q2 are respectively crossed and connected to the gates of the TRs Q1, Q2 and a pair of drains of the TRs Q1, Q2 constitute the output node of data. Accordingly, the TRs Q1, Q2 constitute the current supply TR means as a whole. The data is stored by connecting the drains of the TRs Q11-Q1N to any drain of the TRs Q1, Q2. Accordingly, the data stored in the TRs Q11-Q1N can be recognized according to the drain voltage of the TRs Q1, Q2 and the consumption of power can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a read-only memory device, and in particular to a MOS
) A read-only memory device configured with transistors.

[Prior Art] Conventionally, this type of read-only memory device as shown in FIG. 3 is known. In Figure 3,
1 to N are input terminals, and these input terminals 1 to N are connected to the gates of MOS transistors Qll to QIN whose sources are grounded. QO is a resistor configured as a MOS transistor, and the source of the MO3 resistor QO is connected to the power supply potential Vdd. Data storage is MOS)
The drains of transistors Qll to QIN are connected to MOS resistors QO
This depends on whether or not it is connected to the drain of the That is, if the drains of the MOS) transistors Qll~QIN are connected to the drains of the MO5 resistors QO, when the input terminals 1~N shift to high level, the MO5 resistors QO and the MOS) transistors Qll~ Since current flows through QIN, the drain voltage of MO5 resistor QO will be at a low level. On the other hand, if the drains of the MOS transistors Qll~QIN and the drains of the MO5 resistors QO are not connected, the drains of the MO3 resistors QO maintain a high level, and the drain voltage of the MOS resistors causes the drains of the MOS transistors Q11~ Data D1 written in QIN can be known.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional example, depending on the stored data, the power supply potential V is constantly maintained during the data read period.
Since a current path is formed between dd and the ground terminal, there is a problem in that the power consumption of the memory device increases.

An object of the present invention is to provide a read-only memory device with low power consumption.

[Means, actions and effects for solving the problems] A read-only memory device according to the present invention has a plurality of input terminals,
a plurality of storage elements having a source connected to a first reference voltage source and turned on when selected by a signal supplied to the input terminal; and current supply transistor means having a source connected to a second reference voltage source. , in a read-only memory device in which the storage element and the drain of the current supply transistor means are selectively connected in accordance with data to be stored, the drain and gate of the current supply transistor means are cross-connected to each other, and the drain is connected to the drain of the current supply transistor means; It is characterized in that it is composed of a pair of transistors that turn off when a reference voltage reaches one, and that the drain of the storage element is connected to the drain of one of the pair of transistors in correspondence with the data to be stored.

Once a signal is supplied to the input terminal to access a desired storage element, the storage element is turned on and its drain becomes the first reference voltage. As a result, of the pair of cross-connected transistors, the drain of the transistor connected to the drain of the accessed storage element reaches the first reference voltage and is turned off. On the other hand, since the drain of the transistor not connected to the accessed storage element maintains the second reference voltage, the data stored in the accessed storage element can be determined based on the voltage difference between the pair of transistors. be able to.

In this way, in the read-only memory device according to the present invention, the transistor connected to the accessed storage element is turned off immediately after the start of access to the storage element.
No current path is formed between the first reference voltage source and the second reference voltage source during the data read period, thereby reducing power consumption.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an electric circuit diagram showing the configuration of a first embodiment of the present invention, in which a pair of P-channel MO5) transistors Ql and Q2 whose sources are connected to a power supply potential and whose gates are connected to input terminals 1 to N, respectively. It has connected N-channel MOS) transistors Qll to QIN. The drains of MOS) transistors Ql and Q2 are MOS) transistors Q2.
Ql gates are cross-connected to each other (MOS)
A pair of drains of transistors Ql and Q2 constitute a data output node. Therefore, the above-mentioned MOS transistors Ql and Q2 constitute current supply transistor means as a whole.

Data is stored by connecting the drains of MOS transistors Qll to QIN to which drain of MOS transistors Ql and Q2.

That is, for example, if the drain of the MOS transistor Qll is connected to the drain of the MOS transistor Q1, when the input terminal 1 goes high, the drain of the MOS transistor Q1 is grounded and goes low; ) The transistor Q1 is turned off and current no longer flows. On the other hand, the gate of the N10S transistor Q2 is at a low level, and its drain remains at a high level.

On the other hand, if the drain of MOS transistor Qll is connected to the drain of MOS transistor Q2, when input terminal 1 goes high, the drain of MOS transistor Q2 is grounded and goes low. Although the MOS transistor Q2 is turned off and current no longer flows, the drain of the MOS transistor Q1 remains at a high level. Therefore, MOS) transistor Ql
.

Due to the drain voltage of Q2, MOS) transistor Q11~
The data stored in QIN can be known, and since no current path is formed during the read period, power consumption is also reduced.

FIG. 2 is an electrical circuit diagram showing a second embodiment of the present invention,
The first embodiment is constructed by cascading the first embodiment. Therefore, in the second embodiment, N1 bits of data can be read by designating one input terminal.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram showing the configuration of a first embodiment of the present invention, FIG. 2 is an electric circuit diagram showing the configuration of a second embodiment of the invention, and FIG. 3 is an electric circuit diagram showing a conventional example. be. 1 to N...Input terminal, Ql, Q2...MOS) transistor (current supply transistor means), Qll to QMN...MOS) transistor (storage element), G. ...... Ground terminal (first reference voltage source), Vdd... Power supply potential (second reference voltage source). Patent Applicant NEC Corporation Representative Patent Attorney Kiyoshi Kuwai - - (N $ 1 Ward 1 to T-

Claims (1)

[Claims] a plurality of input terminals, a plurality of storage elements having sources connected to a first reference voltage source and turned on when selected by a signal supplied to the input terminals; and a current supply having sources connected to a second reference voltage source. In a read-only memory device comprising a transistor means, the storage element and the drain of the current supply transistor means are selectively connected in accordance with data to be stored, the current supply transistor means having its drain and gate connected to each other. It is composed of a pair of transistors that are cross-connected and turn off when the drain reaches a first reference voltage, and the drain of the storage element is connected to the drain of one of the pair of transistors in correspondence with the data to be stored. A read-only memory device with special features.