JPH0196889A - Storing circuit - Google Patents

Abstract

PURPOSE:To prevent a large current during the transient period of a circuit from flowing by providing an inverter buffer circuit enabled and controlled by a writing signal in the selecting circuit of a recording circuit having a storing element formed by two sets of inverters. CONSTITUTION:The bit data of the buffer inverter 22 is written through a C-MOS inverter 25 in a memory formed of the storing element of the inverters 9, 10 to which the output and the input of the storing circuit of a bit unit are connected when switching transistors (TR) 27, 28 turned on by a NAND gate 13 operating in response to the row and column selecting signals 52, 57 of the address symbol of the selecting circuit 3 are enabled. When the address signal is not stabilized but the inverter 25 is enabled during the unstable period of the circuit such as the transient state at the time of charging a power, a pulling between the inverters 22 and 10 is not generated which is different from the use of a gate circuit according to the existence of the inverter 25. Accordingly, the large current during the transient period of the circuit is prevented from flowing.

Description

Detailed Description of the Invention Technical Field The present invention relates to a memory circuit, and in particular to a FIFO (First in
First Out) relates to storage circuits such as memory.

Prior Art An example of a conventional memory circuit of this type is shown in FIG.
For simplicity, a circuit for 2 bits arranged in 2 rows and 1 column is shown.

In the figure, each bit-based storage circuit 1 and 2 consists of write selection circuits 3 and 4, memories 5 and 6, and read selection circuits 7 and 8, respectively. .

Each memory 5 and 6 has a pair of inverters 9, 10 and 11
．． 12, the output of inverter 9 is connected to the input of inverter 10, and the output of inverter 10 is connected to the input of inverter 9. The memory 6 also has a similar connection relationship.

Each write selection circuit 3 and 4 has two manual NAND gates 13
and 16, inverters 14 and 17, and transfer gates 15 and 18, respectively.

The Nant gate 13 receives a row write address signal @52 and a column write address signal 57, and the transformer 71 gate 15 is on/off controlled by this gate output and its inverted output by the inverter 14. The old selection circuit 4 also has a similar connection relationship.

Each read selection circuit 7 and 8 consists of one transfer gate and 20, and these transfer gates are controlled on and off by the column read address signal 54 and its inverted output from the inverter 21.

Input data 51 is input to each transfer gate 15 and 18 via inverters 22 and 23, respectively, and each output of each of these transfer gates 15 and 18 is input to memory 5.
and 6 are inputs to corresponding inverters 9 and 11. The output data of each memory 5 and 6 is read data 55 through the corresponding transfer gates 19 and 20.
and 56.

In such a configuration, during a transition such as immediately after power is turned on, the address signal may remain in a state where it is not determined to a specific value until the circuit enters a normal operating state. In such a state, the values of the row write address signal 52.53 and the column write address signal 57 are not determined, and the Nant gate 13.16
Both outputs may become low level. that time,
Since the transfer gates 15 and 18 are turned on, inverters 9 and 10 and inverter 23 are attracted to each other, causing a large amount of current to flow.

Similarly, a large current will flow between the inverters 11, 12 and the inverter 23, and as a result, there is a risk that an extremely large current will flow through the input stage inverter 23.

OBJECTS OF THE INVENTION An object of the present invention is to provide a memory circuit in which a large current does not flow during the transition period of the circuit.

11Ω11 According to the present invention, the memory element includes a memory element configured by connecting an output of a first inverter to an input of a second inverter, and connecting an output of the second inverter to an input of the first inverter. A storage circuit including an inverter buffer circuit connected between an input of the first inverter and a data input terminal, and an enable control circuit that enables and controls the inverter buffer circuit in response to a write control signal. It is characterized by

Actual flow example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and parts equivalent to those in FIG. 3 are indicated by the same symbols.

The transfer gates 15 and 18 in the write selection circuit in FIG. 3 of the conventional example are replaced by inverters 25 and 26 made of C-MOS transistors, and switching transistors 27, 28 and 29 for enabling (activating) the inverters. 30.

That is, input data is applied to the input (common gate of transistors T1 and T2) of a C-MOS inverter 25 consisting of a P-channel transistor T1 and an N-channel transistor T2 via the inverter 22, and is output from the inverter output (common drain). Data is derived. A P-channel MOS transistor 27 for switching is connected in series between the source of the transistor T1 and the positive power supply, and an N-channel transistor 28 for switching is connected in series between the source of the transistor T2 and the ground. . The output of the Nandt gate 13 and its inverted output are applied to the gates of these switching transistors 27 and 28, respectively.

The other write selection circuits 4 have similar configurations.

In such a configuration, the row write address signal @52.
53 and column address signal 57, column read address signal 5
4 are all at low level, both memory circuits 7 and 8 are not occupied or read even if the input data 51 changes.

In this state, when the row write address signal 52 and the column write address signal 57 are selected and become high level, the switching transistors 27 and 28 are turned on, and the C-MOS inverter 25 is enabled. Therefore, input data 51 is input to inverter 22 and C
- It is written into the memory 5 via the MOS inverter 25. At this time, since the row write address signal 53 is at a low level, the C-MOS inverter 26 is in an ice enabled (inactive) state, and therefore no data is written to the memory 6.

If the circuit is unstable such as in a transient state, the address signal is not determined, but in this case the switching transistor 27.2
Even if C-MOS inverters 25, 26 and 8 and 29.30 are both turned on and the C-MOS inverter 25.26 is enabled, the C-MOS
Due to the presence of the inverter, no interaction occurs between the input inverter 22 and the memory inverter 10. Also,
Inquiries with other memory inverters 12 will not occur.

In this way, the write selection circuit uses an inverter buffer that can be freely controlled on and off in place of the transfer gate, and an enable control circuit that controls the inverter buffer on and off according to the write selection signal, and allows each memory to be By connecting the inverter buffer provided in the input inverter to the inverter buffer provided in the input inverter, it is possible to prevent a large current between the input inverter and all the memories.

Even if an inquiry occurs between an individual memory and an inverter buffer corresponding to the memory, the current is small and each inverter of the memory is inverted, so the inquiry disappears instantly.

FIG. 2 is a circuit diagram of another embodiment of the present invention, in which parts equivalent to those in FIG. 1 are designated by the same reference numerals.

In this example, only the 1-bit memory circuit 1 is shown, but it is obvious that the same applies to the other bit memory circuits 2.

In the case of this embodiment, the transistors T and T2 constituting the C-MOS inverter and the switching transistor 2 are
7.28, except that the series connection relationship with the embodiment of FIG. 1 is reversed. That is, C-
MOS inverter transistors T and T2 are connected to the power supply and ground sides, respectively, and switching transistors 27,
28 are respectively connected to the inverter output side.

It is clear that this example also has the same effects as the example shown in FIG.

In the above embodiment, a C-MOS inverter is used to cut off the flow from the memory to the input data side, but in short, it is sufficient to use a buffer whose enable can be controlled by an external control signal. Not only the T-transistor, but also the transistor (
It can be constructed using field effect transistors, bipolar transistors, etc.).

Effects of the Invention As described above, according to the present invention, in the write selection circuit, a unidirectional enable controllable inverter buffer is used instead of a transfer gate, so that the inverter of the memory and the inverter on the input data side can be connected. This has the effect of eliminating the tension between the two and making it possible to prevent a large amount of current.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the invention, FIG. 2 is a partial circuit diagram of another embodiment of the invention, and FIG. 3 is a diagram showing a conventional memory circuit. Explanation of symbols of main parts 1.2... Bit unit storage circuit 3.4...
...Write selection circuit 5.6...Memory

Claims (2)

[Claims] (1) A memory circuit having a memory element configured by connecting an output of a first inverter to an input of a second inverter, and connecting an output of the second inverter to an input of the first inverter. and an inverter buffer circuit connected between the input of the first inverter and a data input terminal, and an enable control circuit that enables and controls the inverter buffer circuit in response to a write control signal. memory circuit. (2) The inverter buffer circuit is an inverter having an input to which write data is applied, an output connected to the input of the first inverter, and comprising first and second field effect transistors of opposite conductivity types. , the enable control circuit is characterized by comprising first and second switching transistors connected in series with the first and second field effect transistors and controlled to be turned on and off according to the write control signal. A memory circuit according to claim 1.