JPS5851358B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, particularly to a semiconductor integrated circuit device suitable for implementation in a sense amplifier circuit of a low power consumption complementary MOS (CMOS) programmable read-on memory (P-ROM). It is something.

P-ROM has three major functions: ``write'', ``read'', and 1-erase, and each operation mode can be switched by selecting the voltage terminal to be used.

Conventionally, this PROM was composed of single-channel transistors, and a sense amplifier for reading out a specific addressed memory was composed of a totem pole circuit as shown in FIG.

In the figure, 1a to 1j are N-channel MOS transistors 2a, 2b are voltage dividing resistors, and 3a.

3b is a power supply terminal to which the first power supply voltage VDD is supplied; 4
a, 4b...4e are the second power supply voltage VG
5a and 5b are power supply terminals (ground terminals) of voltage VSS, 6 is a power supply terminal to which voltage VBB is supplied, and 7 is a memory cell.

A portion 8 surrounded by a broken line indicates a sense amplifier, and a portion 9 surrounded by a broken line indicates a sense amplifier.
is its input terminal, and 10 is its output terminal.

In the circuit configured in this way, each power supply terminal 3 to 6
vI)I)=5v, VGG=12V, respectively.

It operates when VSS=OV, VBB--V is supplied.

Therefore, the signal held in the memory self is 5
It is detected as a signal with an amplitude of v to -5v.

This signal is then sent to the sense amplifier 8 via the input terminal 9.
This sense amplifier 8 receives VGG=1.
It operates at 2V and is a ratio circuit, so
It operates at a low sense level, sets the level at one point in the figure to a low level (L), and is output from the output terminal 10 through the totem pole circuit.

Here, the gate of the MOS transistor lj(%c) which constitutes the 1-tempole circuit operates at 5V=-5V in order to receive the memory signal, and the gate is input to the MOS transistor 111B" from the previous stage. A signal change is detected by a slight change in the current level.

However, since such a circuit requires a multi-power supply circuit, it has the drawback of impairing the power supply operation and low power consumption functions.

In view of the above-mentioned points, the present invention provides a semiconductor integrated circuit device which is designed to solve such problems and eliminate such drawbacks.Hereinafter, the structure thereof will be explained in detail with reference to the illustrated embodiments. .

FIG. 2 is a block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention, and shows an example in which the present invention is applied to a CMOS sense circuit.

In the figure, 11 is an input terminal to which an input signal is applied;
2 is an output terminal 13a from which an output signal is obtained.

13b is a power supply terminal to which voltage VDD=5V is supplied; 14
a and 14b are power supply terminals (ground terminals) with voltage VSS=OV
It is.

15a, 15b and 15c are P-channel MOS transistors; 16at16b and 16c are N-channel MOS transistors;
) transistors 15a and 15b and N-channel MO
S) The transistors 16a and 16b are connected in series between the power terminal 13a and the ground terminal 14a.

In addition, the P-channel MOS) transistor 15c and the N-channel MOS) transistor 16c are connected to the power supply terminal 13b.
and the ground terminal 14b.

Then, P channel MOS transistor 15a and N
A transmission cage composed of a P-channel MOS transistor 15b and an N-channel MOS transistor 16a is inserted between the drains of a CMOS inverter in which channel MOS transistors 16b are connected in series, and these constitute the first inverter. are doing.

In addition, a P-channel MOS transistor 15c and an N-channel MOS transistor 16c are connected in series,
P-channel MOS) transistor 15c gate;
an N-channel MOS forming the first inverter;
) The drain of the transistor 16b is connected to the gate of the N-channel MOS transistor 16c, which is a P-channel MOS transistor 15 forming the first inverter.
These are connected to the drain of a, and constitute a second inverter.

And P channel MOS) transistors 15a and 1
5b and N channel MOS) transistor 16a>
The gates of 16b are connected to the input terminal 11, respectively, and the gates of P
Channel MOS) drain of transistor 15c and N
A connection point of the drain of the channel MOS transistor 16c is connected to the output terminal 12.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

First, in Figure 2, the drain of the C-MOS inverter is connected to the C-MOS inverter.
The mutual conductance of the N-channel MOS transistor 16bD" and the P-channel MOS transistor 15aXXE" is much smaller than that of the CMOS transistor.

The input signal applied to the input terminal 11 is now at a low level.
Suppose that the level changes from "H" to a high level "H".

Here, the N-channel MOS transistor 16bD
" has a large mutual conductance, so an "L" level is immediately generated at its drain, and the P-channel MOS transistor 15c" of the next stage totem pole circuit
Turn on 'ON'.

On the other hand, P channel MOS) transistor 15a'E
The "no drain level" remains at the "H" level because the mutual conductance of the transmission gate is small.

The output level of the next stage changes from a low level "L" to a high level "H" depending on the levels of the N-channel MOS transistor 16b'D" and the P-channel MOS transistor 15aE", which have different conductivity types. become.

As a result, small changes in the input level will cause the sense circuit to operate.

In this way, a high-performance sense amplifier can be realized without impairing the features of the C-MO8 circuit, such as single power supply voltage operation and low power consumption.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

In FIG. 3, the same parts as in FIG. 2 are given the same reference numerals, and their explanation will be omitted.

In the circuit shown in FIG. 2, changes in the input level are quickly transmitted to the output circuit, but this causes the disadvantage that the current in the input inverter continues to flow until the level of the P-channel MOS transistor 15a'E'' changes. The circuit shown in Figure 3 is designed to compensate for these.

That is, in a semiconductor memory device, it is sometimes sufficient to detect an "L" signal or a "H" signal, but in such a case, the above-mentioned disadvantages can be solved by the circuit of the embodiment shown in FIG. can be covered.

This circuit connects the gate of a transmission gate N-channel MOS transistor 16a and the output of a totem pole circuit. In this case, when the output of the totem pole circuit changes from a low level "L" to a high level "XH", N channel MOS) transistor 16a'
Turn on the P channel MOS) transistor 15a.
The level of "E" can be immediately lowered to the low level "L".

Although the present invention has been described above with reference to the case of detecting a low level 9L'', the present invention is not limited thereto (the present invention can also be easily assembled to detect a high level 9L'').

As is clear from the above description, according to the present invention, C-MO can be achieved with a simple configuration without using complicated means.
Since it is possible to obtain a high-performance sense amplifier that does not impair the functions of single power supply operation and low power consumption, which are the features of the 8 circuit, the practical effects are extremely high.

It is also extremely useful in terms of its suitability for integrated circuit technology.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional semiconductor integrated circuit device, FIG. 2 is a block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 3 is a block diagram showing another embodiment of the present invention. FIG. 15a to 15c...P channel MOS transistor, 16a to 16c...N channel MO
S transistor.

Claims (1)

[Claims] 1. A transmission gate made up of a first channel transistor and a second channel transistor is inserted between the drains of a CMOS inverter in which a first channel transistor and a second channel transistor are connected in series. A first inverter, a first channel transistor, and a second channel transistor are connected in series, the gate of the first channel transistor is connected to the drain of the second channel transistor of the first inverter, and A semiconductor integrated circuit device comprising a second inverter formed by connecting a gate of a second channel transistor and a drain of a first channel transistor of the first inverter. 2 The gate of the second channel transistor of the transmission gate constituted by the first channel transistor and the second channel transistor is connected to the drain of the first channel transistor and the drain of the second channel transistor constituting the second inverter. Claim 1 characterized in that the connection point with
The semiconductor integrated circuit device described in .