JPS6196587A - Sense amplifier circuit - Google Patents

Abstract

PURPOSE:To decrease a through electric current and to obtain an inverting output in a current mirror type sense amplifier by connecting mutually the gate of the load transistor to a cross couple. CONSTITUTION:When an N type transistor Q5 for control is on, enters the reading condition, one side bit line is descended toward L in accordance with the contents of a memory cell, and the impressed voltage of an input terminal 11, etc., is reduced. Then, a channel resistance of the N type transistor Q1 for driving is increased, an electric potential of an output terminal 131 rises, the channel resistance of a transistor Q4 out of P type transistors Q3 and Q4 for load and where the gate is connected in a cross mode is increased. Thus, the electric potential of an inverting output terminal 132 is reduced, the channel resistance of the transistor Q3 is decreased, the electric potential of the terminal 131 further rises and goes to an electric power source voltage VDD, the electric potential of the terminal 132 reaches an earth voltage VSS and a through electric current at reading is suppressed to the minimum. An inverting output of a load driving ability equal to the output can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a sense amplifier circuit for a CMO8fi semiconductor memory device, and particularly relates to a sense amplifier circuit for a CMO8fi semiconductor memory device.
This is used in a MOS static type memory circuit.

[Technical background of the invention]

Conventionally, as this type of sense amplifier circuit, a current mirror type as shown in FIG. 4 has been widely used. This sense amplifier circuit is composed of N-channel type drive transistors Q1+Q2, P-channel type load transistors Q31Q4, and a control transistor Q5 whose conduction is controlled by a control signal C8. A bit line and an inverted bit line of the memory cell array are connected to the gate side input terminal 11 and the inverted input terminal 12 of the drive transistors Ql and Q2, respectively.

Next, the operation in the above configuration will be explained. First, when the control signal C8 supplied to the gate of the control transistor Q5 becomes high (°'H'') level, the transistor Q6 is turned on and the sense amplifier circuit enters the operable state.

Before reading data from the memory, the input terminal 1 and the inverting input terminal 12 are kept at the same potential, and for convenience of explanation, the input terminal 11 and the inverting input terminal 12 are each precharged before the read operation. When the read operation starts, a potential difference is generated between the bit line and the inverted bit line depending on the contents (stored information) of the memory cell, and this potential difference is maintained at the input terminal 11 and the inverted bit line. is applied to input terminal 12. Now input terminal 11
Assuming that the voltage applied to the terminal decreases from the "H" level toward the low (L) level, the channel resistance of the transistor Q1 increases, and the connection point Nr (output terminal 13) between the transistors Ql and Q3 increases. The potential is “H” level (
', the voltage rises towards the source voltage vDD). At this time, the channel resistance of the transistor Q2 is low because the inverting input terminal J2 is at the tHs level, and the bias node N2 is held at the IIL# level. Therefore, the channel resistance of the transistor Q3 is low, and the output It functions to further raise the terminal 13 to the ``H'' level. Therefore,
A signal of ``H# level'' is obtained from the output terminal 13 due to the relationship between the channel resistances of the transistors Q1 and Q3.

On the other hand, when the inverting input terminal 12 falls toward the "L#" level, the channel resistance of the transistor Q2 increases, so the potential of the bias node N2 increases, and the channel resistance of the transistor Q3 increases. At this time, The channel resistance of the transistor Q1 is low because the input terminal IJ is at the IIH11 level. Therefore, a signal at the "L#" level is obtained from the output terminal 13.

Note that the above-mentioned operation applies to input terminal 1 and inverting input terminal 2.
Although the explanation has been made on the assumption that 2 and 2 are recharged to the 'H' level before the sensing operation, the same holds true even if the battery cannot be fully charged.

[Problems with background technology]

By the way, in the current mirror type sense amplifier circuit shown in FIG. There is a drawback that a through current flows through the ground point. Such a through current becomes a problem especially when used in a CMOS static type memory circuit that requires low power consumption.

In addition, in the current mirror type sense amplifier circuit described above,
Bias node N! Since the voltage amplitude of N2 is small, an inverted output cannot be obtained from this node N2.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide an excellent sense amplifier circuit that can reduce the through current on the bias node side that is unavoidable in current mirror type sense amplifier circuits, and can also provide an inverted output.

[Summary of the invention]

That is, in the present invention, in order to achieve the above object, the gates of each load transistor are connected to one end of the opposing load transistor in a cross-coupled manner.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. An input terminal 11 and an inverting input terminal 2 are connected to the gates of the N-channel drive transistors Ql and Q2 in FIG. 1, respectively. Above transistor Q
One end of l-(h is connected in common, and an N-channel type control transistor Qs whose conduction is controlled by a control signal C8 is connected between this common connection point and a ground point. A P-channel type load transistor Q3=Q4 is connected between the other end and the power supply '/DD.A connection point between the transistors Q2 and Q4 is connected to the gate of the transistor Q3.
At the gate of 4, the above transistor Q! The connection point between Q3 and Q3 is connected to a cross couple. An output terminal 131 is connected to the connection point between the transistors 9 and Q3, and an inverting output terminal 132 is connected to the connection point between the transistors Qz and Q4.

Note that, when applied to a semiconductor memory device, the input terminals 1) and 1 inverted input terminal 12 are respectively connected to a pit line and an inverted bit line to which a plurality of memory cells are connected.

Next, the operation in the above configuration will be explained. now,
Input terminal JJ, inverting input terminal 12 (d.

It is assumed that the control transistor Q is at the same potential and at the "H# level" before the read operation from the memory cell.
When the control signal C8 at the sK"H" level is supplied and the transistor Q6 is turned on, the sense antenna circuit enters the operable state. Then, when a read operation is started, either the bit line 66 or the inverted bit line falls toward the "L#" level depending on the content (stored information) of the memory cell, and this voltage is applied to the input terminal 1 no 1
It is applied to the inverting input terminal 12.

Now, assuming that the voltage applied to the input terminal 11 decreases,
The channel resistance of transistor Q1 increases, and output terminal 1
The potential at node 31 begins to rise toward the "H" level. As a result, the channel resistance of transistor Q4 increases, and the potential at inverting output terminal 32 decreases.As a result, the channel resistance of transistor Q3 decreases. Output terminal 73
1 is further raised to the "H" level.

When the potential difference between the input terminal JJ and the inverting input terminal 12 becomes sufficiently large, the output terminal 13. reaches the VDD level, and the inverting output terminal 132 reaches the Vss (ground) level.

On the other hand, when the voltage applied to the inverting input terminal 12 decreases, the channel resistance of the transistor Q2 increases, and after a circuit operation that is in a symmetrical relationship with the above explanation, the output terminal 131 is finally connected to VII8 (ground). level, and the inverting output terminal 32 reaches the vDD level.

In this way, in the sense up circuit shown in FIG. 1 above, the load transistor Q! = Drive transistor Q2 whose gates are opposite to each other.

Since the output terminal 1319 is connected to the drain of
Van r VgB), and the through current can be minimized. In addition, an inverted output with the same load driving ability as the ・output can be obtained.

In the above embodiment, the case where the N-channel type control transistor Q5 is provided on the ground side is explained, but as shown in FIG.
Even if it is provided on the power supply Vt1D side, the same operation can be performed and the same effect can be obtained. Further, the drive transistor Q1. We have explained the case where Q2 is an N-channel type and the load transistors Q3 and Q4 are P-channel types, but it is also possible to configure the drive transistor to be a P-channel type and the load transistor to be an N-channel type, and to reverse the polarity of the power supply. Of course.

FIG. 3 shows an embodiment of the pond of the present invention, in which the sense amplifier circuit fj shown in FIG. 1 is connected in two stages in cascade. The output signal and the inverted output signal of the first-stage sense amplifier circuit 14 constituted by transistors Ql to Q5 are respectively supplied to the gates of drive transistors Qt and Qa of a dual-role sense amplifier circuit J5.

A control transistor Q]1 whose conduction is controlled by a control signal CS is connected between a common connection point on one end side of these transistors Qy=Qs and a ground point, and the transistors Q7. QI
A load transistor Q9.1 is connected between the other end of the Q9. Qlo is connected. The gate of the transistor Q9 is connected to the connection point between the transistors Q8 and Qto, and the gate of the transistor Qso is connected to the connection point between the transistors Q7 and Q9.

An output terminal 161 is connected to the connection point between the transistors Q7 and Q9, and an inverting output terminal 162 is connected to the connection point between the transistors Qs and Qlo.

In the above configuration, each sense amplifier circuit 1
Since the operation of 4.15 is the same as that of the circuit shown in FIG. 1, detailed explanation thereof will be omitted.

According to such a configuration, since two-stage amplification is performed, the sensitivity of the sense amplifier can be increased.

It goes without saying that the same effect can be obtained by cascading two stages of the circuit shown in Fig. 2, and it goes without saying that the polarity of the transistors and the polarity of the power supply may be reversed. .

〔Effect of the invention〕

As described above, according to the present invention, an excellent sense amplifier circuit can be obtained which can reduce the through current on the h bias no-P side, which is inevitable in a current mirror type sense amplifier circuit, and can also obtain an inverted output.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a sense amplifier circuit according to an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams for explaining other embodiments of the invention, and FIG. 4 is a diagram showing a conventional sense amplifier circuit. FIG. 3 is a diagram showing an amplifier circuit arrangement. 1no...input terminal, 12...inverting input terminal, 131
...output terminal, 132...inverted output terminal, Ql-Q
s...first to fifth transistors, Qa...fifth transistor, vDD...power supply, C8...control signal. Applicant's representative Patent attorney Takeshi Suzue Syllable 1 Figure 2 Figure 3 Figure 24

Claims (4)

[Claims] (1) First and second gates of the first conductivity type, each having a gate connected to an input terminal and an inverting input terminal, and one end connected in common.
a third transistor of a second conductivity type connected between the other ends of the first and second transistors and one of the power supplies, respectively;
, a fifth transistor of a first conductivity type connected between a common connection point on one end side of the first and second transistors and the other side of the power source and whose conduction is controlled by a control signal, A gate of the transistor is connected to a connection point between the second and fourth transistors, a gate of the fourth transistor is connected to a connection point between the first and third transistors, and a connection between the first and third transistors is formed. A sense amplifier circuit characterized in that it obtains an output from a point and obtains an inverted output from a connection point between the second and fourth transistors. (2) A sense amplifier circuit characterized in that a plurality of sense amplifier circuits according to claim 1 are connected in cascade. (3) first and second transistors of a first conductivity type whose gates are respectively connected to the input terminal and the inverting input terminal and whose one ends are commonly connected and connected to the other side of the power supply; A third and fourth transistor of a second conductivity type connected to the other end of the transistor and whose other ends are commonly connected, and a control device connected between a common connection point on the other end side of these third and fourth transistors and one of the power sources. The second conduction is controlled by the signal.
a fifth transistor of a conductivity type, the gate of the third transistor is connected to the connection point of the second and fourth transistors, and the gate of the fourth transistor is connected to the connection point of the first transistor.
, connected to the connection point of the third transistor, and obtains an output from the connection point of the first and third transistors, and obtains an inverted output from the connection point of the second and fourth transistors. amplifier circuit. (4) A sense amplifier circuit characterized in that a plurality of sense amplifier circuits according to claim 3 are connected in cascade.