JPS601708B2 - sensing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to highly sensitive sensing circuits used in integrated memories and the like.

Fritub is a well-known sensing circuit. Flop-type sensing circuits are well known, and an example in which high sensitivity is achieved by using the flip-flop / board as an input/output terminal and providing a switch between the flip-flop and the power supply terminal is the lEEE JOUR.
NALOFSOLIDSTATEC 瓜CL TS・VO
LUME SC-・〇, Nkawa MBER 5, pp225
~pp261 (October 1975 self-published paper), Pe
life's circuit br 0 -Tra
The sensing circuit shown in FIG. 1 is described in the ship's CellMOSRAM'sr.

Flip. Flop-type sensing circuits require that transistors forming a pair have substantially the same performance;
Conversely, the greater the difference in performance, the worse the sensitivity. In particular, the difference in threshold value between the cross-coupled transistor pair of a flip-flop has the most sensitive effect on sensitivity. An object of the present invention is to increase the sensitivity of a flip-flop type sensing circuit.

According to the present invention, it is possible to obtain a high-sensitivity sensing circuit in which the difference in threshold value between a pair of cross-coupled transistors in a flip-flop type sensing circuit has relatively little effect on sensitivity, and which is easy to manufacture.

That is, first and second transistors each have one drain terminal connected to the other gate terminal, and a first
a third transistor whose drain terminal is connected to the source terminal of the transistor; a fourth transistor whose drain terminal is connected to the source terminal of the second transistor; and a fourth transistor whose source terminal is connected to the drain terminal of the first transistor. a sixth transistor whose source terminal is connected to the second transistor terminal; and a seventh transistor whose drain is connected to the sources of the third and fourth transistors.
The drain terminals of the fifth and sixth transistors are both connected to the first power supply, the gates of the fifth and sixth transistors are both connected to the second clock terminal, and the drain terminals of the fifth and sixth transistors are both connected to the second clock terminal. the gate terminals of the fourth and seventh transistors are both connected to the first clock terminal;
The source terminal of the seventh transistor is connected to the second power supply, the drain terminal of the first transistor is connected to the first signal terminal, and the drain terminal of the second transistor is connected to the second signal terminal. A sensing circuit is obtained which is characterized by the following. Next, an explanation will be given with reference to the drawings, taking an n-channel MOS transistor as an example of the transistor.

FIG. 1 shows a conventionally known sensing circuit, in which differential inputs D and D are input, and then the transistor Q3 is turned on by the clock J.
4 begins to conduct slowly, and the cross-coupled transistor Q. , Q2, the input signal is amplified to some extent, and one of the transistors (let's say Q) becomes more conductive than the other transistor (let's call it Q2).

When transistors Q5 and Q6 are then turned on by clock ◇2, the drain of Q approaches approximately the low level V2 potential, while the drain of Q2 approaches the high level V, potential. In the end, the minute differential input is multiplied by the difference between the power supply voltages V and V2. Therefore, it has extremely high sensitivity, but if transistor Q2 is higher than transistor Q by △V at its threshold value, when a lower differential signal △V' is input, that is, terminal D is higher than terminal D. Even if a higher input is received by AV', the output terminal D will be at a high level and terminal D will be at a low level due to the threshold value difference between transistors Q and Q2. So the sensitivity is about 4
Only V gets worse. Of course, each transistor Q, ~Q6
Consideration has been taken on masks and processes to reduce the difference in threshold values.

However, since the transistors Q and Q2 are kept in opposite states, one being in a conductive state and the other in a non-conducting state, this state may be maintained for a long time depending on the mode of use. In this case, the transistor in the conductive state becomes hotter and the threshold value changes. Therefore, in practice, a threshold difference between transistors Q and Q2 is likely to occur, resulting in deterioration of the sensitivity of the sensing circuit. FIG. 2 shows an embodiment of the present invention that compensates for the above drawbacks. The point that pull-up transistors Q5 and Q6 are connected to the drains of cross-coupled transistors Q, Q2 is the same as in Figure 1, but the sources of transistors Q, Q2 are connected to transistors Q and Q4, respectively. , Q7 to the low level power supply V2 is a feature of the present invention.

The source of transistor Q is at point A, the source of transistor Q2 is at point B, and the drain of transistor Q7 is at point C. Usually A, B
The potential at the point is at the low potential source V2 level, but if D and D are precharged to a constant level Vp between the power supplies V and V2 prior to inputting the differential signal, the potential at one point A and B ( V.A.
, VB) is a bricharge. They are charged up to a level lower than the level by the threshold values of the transistors Q, Q2 (denoted as VT, Vr2, respectively). That is, it is charged up to VA=Vp-VT, VB=Vp-VT2.

Therefore, suppose that the dark value of transistors Q, , Q2 is △V=VT
, -VT2, the gate potential seen from the source potential of each transistor is still biased to the threshold value.

Figure 3 shows a schematic diagram of the waveforms of each part. If a minute differential signal is input in the above state (assuming that D is at a slightly higher level than ○), transistors Q, ,
Regardless of the difference in threshold value of Q2, the transistor Q2
The transistor Q becomes closer to a conductive state.

Next, due to the clock, transistors Q, Q, and Q7 begin to conduct, and the potentials at nodes A and B begin to drop slowly, but transistor Q2 maintains a relationship closer to conduction than transistor Q, and there is a cross-coupling between them. transistor Q
,, The potential difference between the terminals D and O is increased by the positive feedback increasing action of Q2 and the feedback action from the source side due to the temporary rise in potential at point C. Next, when the transistors Q5 and Q6 are made conductive by the clock 2, the terminal D becomes approximately at the high potential V, and the terminal D becomes approximately at the low potential V2.

Note that the higher the conductance ratio of the transistors Q, (Q2), Q3 (Q4), and Q7, the higher the sensitivity will be. do not have.

For example, a ratio of 10:2:1 is desirable. However, the transistor Q7 is common to a plurality of sense amplifiers, and only one transistor Q7 is required. Therefore, in a circuit that requires a large number of sense amplifiers such as a memory array, the transistor Q
The area occupied by the chip No. 7 is negligibly small per sense amplifier, and the area occupied by the sense amplifier is substantially determined by the transistors Q, -Q6 and their arrangement. Second
An embodiment in which equal coupling capacitances CA and CB are introduced between the input terminal D and the node A and between the input terminal D and the node B in the figure will be described. Coupling capacitances CA and CB are at node A
, B, and if the input capacitance connected to input terminals ○ and D, such as the information output line of a capacitor memory, is sufficiently large compared to CA and CB, the input sensitivity should be nearly doubled. It can be improved. That is, if the input terminal D becomes 5 mV higher than O due to the differential input signal, the node A becomes about 5 mV higher than B at the same time. As a result, the gate-source voltage of transistor Q is 5 mV lower than the threshold of Q, while the gate-source voltage of transistor Q2 is 5 mV higher than the threshold of Q2, which is relatively The voltage difference between the gate and source of transistors Q and Q is l
Doubles to owV. As explained above, it will be understood that according to the present invention, a highly sensitive sensing circuit can be obtained in which the threshold difference between the cross-coupled transistors Q, Q2 hardly affects the sensitivity. The idea of the present invention is to connect the sources of two cross-coupled transistors to a low-level power supply through separate transistors, and to connect a coupling capacitor between the drains and sources of the two cross-coupled transistors. It is claimed that the threshold value of the two transistors does not affect the sensitivity, and it is applicable to many circuit types in addition to the embodiments, so it is extremely useful in practical use.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional sensing circuit, Fig. 2 is a circuit diagram of a sensing circuit according to an embodiment of the present invention, and Fig. 3 is a circuit diagram of the sensing circuit shown in Fig. 2. This is the approximate waveform of In the figure, Q. ~Q, Q side Q7...transistor, D,
D...Signal status, G,, J2...Clock terminal, V,...
. . . indicates a first power supply, V2 . . . indicates a second power supply, respectively. 1 picture, 2 pictures, 3 pictures

Claims (1)

[Claims] 1 first and second transistors with one drain terminal connected to the other gate terminal; a third transistor with the drain terminal connected to the source terminal of the first transistor; and a source terminal of the second transistor. a fourth transistor whose drain terminal is connected to the drain terminal of the first transistor; and a fifth transistor whose source terminal is connected to the drain terminal of the first transistor.
a sixth transistor whose source terminal is connected to the drain terminal of the second transistor; a seventh transistor whose drains are connected to the sources of the third and fourth transistors; The drain terminals of the transistors are both connected to the first power supply, the gate terminals of the fifth and sixth transistors are both connected to the second clock terminal, and the gate terminals of the third, fourth and seventh transistors are both connected to the first power supply. The source terminal of the seventh transistor is connected to the first clock terminal, the source terminal of the seventh transistor is connected to the second power supply, the drain terminal of the first transistor is connected to the first signal line, and the drain terminal of the second transistor is connected to the first signal line. Second
A sensing circuit characterized in that it is connected to a signal line of.