JPS63108570A - Burst error display device - Google Patents

Abstract

PURPOSE:To quantitatively recognize a burst error by counting the number of the successively generating states of 'the presence of an error' based on the state of an error flag and displaying the number of generations to a burst error length on a graph. CONSTITUTION:The error flag outputted from an error detecting circuit 2 is stored sequentially in a flag memory 4 throughout one track. Then, this is sequentially read and the 'presence of the error' is discriminated by a counting and discriminating circuit 6. When at least >= two states of the 'presence of the error' continue, it is defined to be the burst error and counted and the counted value is outputted to a display frequency memory 8 on the burst of the set range of a reference burst length setting circuit 7. Then, the frequency to the generated burst error length generated in a display device 11 through a display control circuit 9, a displaying frame memory 10 and quantitatively recognized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a burst error display device used as a digital audio device such as a digital audio recorder or a digital disk playback device, or as a measuring device thereof.

(Behind the Invention) Conventionally, in digital audio equipment, such as digital audio tape recorders, it has been difficult to determine the location of a burst error, for example, whether a burst error is occurring due to an error in data along a track, or whether a burst error is occurring across a track. It has been desired to detect whether a burst error has occurred based on the presence of erroneous data.

However, burst error detection in the past has only been carried out by viewing the magnetic tape with a magnetic magnifying glass or a microscope, and there is a problem in that it is not possible to objectively determine burst errors as described above.

(Object of the Invention) The present invention has been made in view of the above, and provides a burst error display device capable of solving the above problems, quantitatively detecting burst errors, and recognizing them on an image. The purpose is to

(Means for achieving the purpose) The present invention was constructed as follows to achieve the above object.

A first flag storage unit that stores an error flag output from an error detection circuit that detects a code error in reproduced data, and a storage error flag read from the first flag storage unit to determine whether or not the state is “error present”. During a period during which the "error present" state detected by the first determining means continues multiple times or more, the number of occurrences of the "°° error present" state is counted, and an annotation is performed. When the count is greater than or equal to a predetermined value: 1) A first counting/discriminating means for outputting the count of the number of occurrences and a first display means for displaying the output from the counting/discriminating means were provided.

Further, the first flag storage means stores information on the playback data corresponding to the error flag, and the first display means stores the output from the counting/discriminating means and the first count value output from the counting/discriminating means. Position information for the error flag may also be displayed.

By configuring as described above, the count value from the first counting/discrimination circuit is a count value that counts the number of occurrences of the "error present" state during a period in which multiple or more "error present" states occur consecutively. is displayed on the first display means, so burst errors can be detected in a constant manner.

Furthermore, a second flag storage unit stores an error flag output from an error detection circuit that detects a code error in the reproduced data, and stores position information of the reproduced data corresponding to the error flag; a second discriminating means for discriminating whether or not there is an error from the storage error flag read from the means; and determining a discriminating output from the second discriminating means and determining a position according to the position information of the reproduced data corresponding to the discriminating output. A third display means for displaying on the top may be provided.

In this case, the determination output of "error present" and "no error" by the second determination means is displayed on the third display device at a position on the third display device according to the position information of the playback data corresponding to the determination output. Therefore, burst errors can be quantitatively detected from the display on the third display device.

(Example of the invention) The present invention will be explained below using examples.

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention, and is an example of the case where the present invention is applied to a digital audio tape recorder.

Reference numeral 1 designates a digital signal processing circuit of a digital audio tape recorder, which includes an error detection circuit 2 for detecting code errors in reproduced data reproduced from a magnetic tape, and an error correction circuit 3. The digital audio chip recorder uses a double Reed-Solomon code error correction code, and the error detection circuit 2 outputs Cl
The flag, C2 flag, and auxiliary flag are output.

The C1 flag is a detection output obtained by performing error detection for each block [32 symbols (1 symbol = 1 byte)] in the order of manual input to the error detection circuit 2.

4 sequentially outputs the Cl flags output from the error detection circuit 2.
This is a flag memory that stores data over one track (128 blocks), and a table of Cl flags for at least one track is formed in the flag memory 4. For example, a table is formed by setting the block number on the magnetic tape at the time of generation of the Cl flag as an address and setting the element data as the data of the C1 flag. In addition, in this example, the data of the 01 flag in the case of “no error” is [
000], Cl flag data in case of “1 symbol error” is [001], C in case of “2 symbol error”
The data of the l flag is shown as [011], and the data of the Cl flag in the case of "an error of three or more symbols" is shown as [111].

Reference numeral 5 denotes a discrimination circuit that discriminates whether or not there is an error based on the stored contents read from the flag memory 4, and outputs a pulse in response to the Cl flag when there is an error. Reference numeral 6 denotes a counter that counts two or more consecutive output pulses output from the discrimination circuit 5, and compares the counted value of this counter with the set value of the standard burst length setting circuit 7, and determines whether the counted value of the counter is the standard. The first set by the burst length setting circuit 7
,'S! .

It is a counting/discrimination circuit that outputs the counted value of the counter when it exceeds a fixed value and is below a second set value, and the reference burst length setting circuit 7 is configured to set the first and second set values, and also displays a display as described below. The number of tracks to be recorded is set.

8 is a display frequency memory that sets the frequency for the same count value as "+1" when the same count value output from the counting/discrimination circuit 6 is input; for example, the count value output from the counting/discrimination circuit 6; The memory contents at the same address are incremented by "+1" by outputting the same count value.

Each count value read from the display frequency memory 7, that is, the frequency data for the burst length, is supplied to the display frame memory IO via the display control circuit 8 and stored therein.
The frequency with respect to the burst length is displayed as a histogram on a display device such as T.

In addition, 12 is a timing circuit, which detects an error every time the input of l block is read, and in synchronization with this, controls the timing of reading the 01 flag into the flag memory 4, and controls the timing of discrimination in the discrimination circuit 5. This is a timing signal generation circuit that outputs a timing signal that controls the counting timing and comparison timing in the counting/discriminating circuit 6.

In one embodiment of the present invention configured as described above, the error detection circuit 2 detects blocks 8l, 82...A128 of track A on the magnetic tape 20 shown in FIG. 2, blocks B1 . Error detection is performed sequentially in the order of B2...BI28, and the Cl flag output from the error detection circuit 2 is sequentially stored in the flag memory 4 over one track. Here, the discrimination circuit 5 to the display frame memory 10 are constituted by a computer and a memory provided therein, and the operation of this embodiment will also be explained with reference to FIG. 3 using a program stored in the RAM of the computer. The contents of the Cl flag stored in the flag memory 4 are sequentially read out and sent to the discriminating circuit 5.
In step b, it is determined whether or not there is an error. This determination is made by determining that there is an error in all cases where the bit content of the Cl flag is other than [000], as described above.

When the discrimination circuit 5 determines that there is an error, it is determined whether the count value of the counter of the man-hour/discrimination circuit 6 is greater than or equal to "1", and when the count value of the counter is greater than or equal to "1", “+1” is added to the count value of the counter (step d)
, if the count value of the counter is not greater than "1" in step C, step d is bypassed and the C1 flag is set to 1.
Stapling a to d is performed over tracks (step e). Once step C is followed by step e
is executed when the state of "error exists" does not occur at least "2" times in a row, and in this example, the case where the state of "error exists" occurs at least twice or more is considered to be a burst error. Step C and Step d
When is executed, a burst error has occurred.

When it is determined in step b that the read Cl flag is "no error", it is determined in step C whether the counted value of the counter is greater than or equal to "2" FL (step f
), when the count value of the counter is determined to be "2" or more in step f, it is determined whether the count value of the counter exceeds the lower limit value set by the reference burst length setting circuit 7 following step f. (step g), and if it exceeds the lower limit, following step g, it is determined whether it is less than or equal to the upper limit set by the reference burst length setting circuit 7 (step h). If it is determined that the burst error is below, it means that the generated burst error exceeds the lower limit value set by the reference burst length setting circuit 7 and is less than the upper limit value, and in this case, following step h, the display frequency memory 8 The frequency for the corresponding burst error length is increased by "+1" (step i). Therefore, in the state of step i, the latest frequency for the burst error length is stored in the display frequency memory 8.

Following step i, the count value of the counter is cleared (
Step j). When the count value of the counter is not 2 or more in step f, is less than the lower limit of the reference burst length in step g, or exceeds the lower limit of the reference burst length in step h, steps f to j are executed; Step g to step j is executed, or step h to step j is executed.

Following step J, step e is executed, and step a is continued until the Cl flag is read for one track.

b and fj are executed, and this is repeated for the set number of tracks set by the reference burst length setting circuit 7 (step k). As a result, the display frequency memory 8 stores the frequency for the burst error length over the set number of tracks, and this memory content is stored in the display frame memory IO under the control of the display control circuit 9. is,
As shown in FIG. 4, the display device 11 displays the frequency with respect to the burst error length in the form of a bar graph.

Therefore, the frequency of occurrence of each burst error length can be detected quantitatively.

Next, a modification of the embodiment of the present invention will be described.

In this modification, the track number and block number (hereinafter referred to as position information) from which the detected C1 flag was obtained when storing the 01 flag are also stored in the flag memory 4. In addition, the display frequency memory 8 is omitted, and the output of the counting/discrimination circuit 7, that is, the count value of the counter and the information on the generation position of the count value, are stored in the display frame memory 10 under the control of the display control circuit 9. The burst error length and its position information are displayed on the display device 11. The other configurations are the same as in the embodiment of the present invention.

The operation of the modified example described above is as shown in FIG. 5. When the count value of the counter is less than 1 in step C in FIG. 3, the position information is stored in the flag memory 4 as the Cl flag. correspondingly stored (step m)
, and subsequent to step m, the count value of the counter is incremented by +1" (step d).

Here, step m to step d are executed, and even when a burst error does not occur, the count value of the counter is “+”
1'', but in this case step g-1 is bypassed and steps f to j are executed, so there is no substantial problem.

Furthermore, step h in FIG. 3 is omitted, and step i
Instead, following step g, the generated burst length 1-, that is, the count value of the counter and the position information stored in step m, are stored in the display frame (step n), and the generated burst error length and the generated burst error length are displayed on the display device I+. Its location information will be displayed.

Therefore, according to this modification, the length of the generated burst error, the track number and block number where the error occurred are displayed, so that the length of the generated burst error can be quantitatively detected.

Next, other embodiments of the present invention will be described.

FIG. 6 is a block diagram showing the configuration of another embodiment of the present invention, and the same components as those in FIG.

The C1 flag output from the error detection circuit 2 and the C1 flag output from the error detection circuit 2
The position information for the l flag is stored in the flag memory 48, and the contents stored in the flag memory axis are read out, and the determination circuit 5 determines whether or not the C1 flag is an error for 61 flags. The memory contents stored in the flag memory 48 are read out, and the position information and position therein are:
, ql +'11i%l and the information from the discriminating circuit 5 as to whether or not the 1 flag is an error are displayed in the display frame memory IOA; The contents are displayed on the display device 11 with one track as one line, and when a predetermined number of tracks are displayed, scrolling is performed to erase the track with the lowest number.

Therefore, in another embodiment of the present invention configured as described above, one track is defined as one line as shown in FIG.
The error status of each block is displayed at the position corresponding to the block.

An example of this is shown in FIG. 7, when an "X" is displayed, it indicates that all blocks of the track are in error. Also, when it is displayed like "Y", it indicates that two blocks of error have occurred perpendicularly to the tracks over three tracks, and when it is displayed roughly like "Z", it means that there is a magnetic error that spans at least five tracks. This shows a case where an error occurs over a width of three blocks along the length of the tape.

Therefore, in the case of X, there is a scratch on the entire track 1, and in the case of Y, there are 3
This is a case where there are scratches between tracks and perpendicularly to the track, and in the case of Z, there are 3 scratches across 5 or more tracks.
Even in cases where scratches occur in the longitudinal direction of the magnetic tape over the width of the block, the state of occurrence of burst errors can be seen as an image.

(Effects of the Invention) As explained above, according to the present invention, it is determined from the state of the Cl flag whether or not there is an "error" state, and the "error" state is continuously maintained. Since the number of occurrences of the "error present" state during a period is counted and the counted value is displayed when the counted value is greater than or equal to a predetermined set value, the burst error length can be quantitatively displayed. Also, it determines whether or not there is an error in the C1 flag, and displays information as to whether or not the Cl flag is an error at the position relative to the position information based on the position information and information on whether or not the Cl flag corresponding to the position information is an error. Therefore, the burst error length and its direction can be viewed as an image from the display on the display device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 and FIG. 4 are diagrams for explaining the operation of an embodiment of the present invention. FIG. 3 is a flowchart for explaining the operation of one embodiment of the present invention. FIG. 5 is a flowchart of a modification section for explaining the operation of a modification of the first example of the present invention. FIG. 6 is a block diagram showing the configuration of another embodiment of the present invention. FIG. 7 is a diagram for explaining the operation of another embodiment of the present invention. 2. Error detection circuit 4 and 4A: Flag memory 5
: Discrimination circuit 6: Counting/discrimination circuit 7: Reference burst length setting circuit 8: Display frequency memory 9 and 981 display; & (I control circuit 10 and 108: Display frame memory 11: Display device patent applicant stock Company Kenwood 31,°r11:: Fig. 1 Fig. 2 □4□ Hi-Store No. 31-11 Fig. 5 Fig. 6 Fig. 7 + 2 ------- 128 hand b'' Ne+l? Ordinary book (method) % formula % 1. Display of the case Patent Application No. 255035 of 1985 2. Name of the invention Burst error display device 3. Person making the amendment Relationship with the case Patent applicant address Shibuya, Tokyo Ward Shibuya 2-17-5 Name (35
9) Kenwood Co., Ltd. 5, subject to amendment

Claims (4)

[Claims] (1) A first flag storage unit that stores an error flag output from an error detection circuit that detects a code error in reproduced data, and a storage error flag read from the first flag storage unit that indicates an “error exists” state. a first determining means for determining whether or not there is an error; and a period during which the "error present" state detected by the first determining means continues multiple times or more;
a first counting/discriminating means that counts the number of occurrences of the "error" state and outputs a counted value of the number of occurrences when the counted value is equal to or greater than a predetermined value; and an output from the first counting/discriminating means. 1. A burst error display device comprising: first display means for displaying. (2) The first display means is provided with display frequency storage means for updating and storing the frequency for each of the same count values, and displays the frequency for each count value. A burst error display device according to scope 1. (3) a second flag storage unit that stores an error flag output from an error detection circuit that detects a code error in the reproduced data, and also stores position information of the reproduced data corresponding to the error flag; A second determining means determines whether or not the state is "error present" based on the memory error flag read from the means; and the "error present" state detected by the second determining means is consecutive for a plurality of times or more. During the period, count the number of times the “error” state occurs,
and a second counting/discriminating means for outputting the counted value of the number of occurrences when the counted value is greater than or equal to a predetermined value; and second display means for displaying position information for the first error flag. (4) a second flag storage unit that stores an error flag output from an error detection circuit that detects a code error in the reproduced data, and also stores position information of the reproduced data corresponding to the error flag; a second discriminating means for discriminating whether or not there is an error from the storage error flag read from the means; and a discriminating output from the second discriminating means, and a position according to the position information of the reproduced data corresponding to the discriminating output. A burst error display device comprising: a third display means for displaying on the top of the burst error display device.