JPS63108442A - Data storage circuit - Google Patents

Abstract

PURPOSE:To decrease the load of a CPU and to improve a display speed by performing the data writing and reading to a video RAm composed of an S/P circuit, a latch circuit, a sector and a memory plane without depending on the CPU. CONSTITUTION:By an S/P converting circuit 11, a pallet number group on data signal lines S0-S3 is converted to 8 bit parallel data. Further, latches 21-24 output these 8 bit data to a selector 30 as D00-D03. A writing control part 50 respectively writes outputs D00-D03 of the latch circuits 21-24 into 000-600 addresses of memory planes 41-44 as writing data d00-d03. A reading control circuit 60 reads successively the pallet number group of 4 bit constitution from the same bit from the same bit position in the area having the same low order addresses 00, 01... in respective memory planes 41-44. Namely, pallet number groups b00-b03, b10-b13 and b20-b23... are successively read and supplied to a color look-up table.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to data storage circuits used in graphic display devices and the like.

Prior art graphic display devices use bitmap type video RAM (VRAM) as the display storage circuit.

For example, in a Videotex terminal, coloring control data sent as serial data from a center station is converted into parallel data groups of 4 bits each (bo. to ), (b
+. ~b1yu), (bZ.~b z,,)...
By converting to , 32 types of 4-bit pallet numbers are restored. The CPU 2 performs bit uffing on the 4-bit pallet number and stores it in the VRAM.
Write on a. This VRAM3 consists of four memory planes 3° to 3 which store only specific bits of each pallet number.
．． It consists of That is, as illustrated in FIG. 3, the O bit in each pallet number is assigned to the memory plane 3° to which addresses from (OOO) to (199) are assigned, and the 1st bit is assigned to address (200). from(
399) Memory plane with address of address 3. In this case, the second bit is in the memory plane 3□ having addresses from (400) to (599), and the third bit is in (
They are respectively stored in the memory plane 33 having addresses from address 600) to address (799).

In the sequential readout for display by the readout control circuit 4, a 4-bit pallet number group (b(10"' bo:l)
, (b+o~b+3) , (bZO~bZ3)
. . . are repeatedly read out in sequence.

Problems to be Solved by the Invention In the above conventional graphic display device, the CP
Since U performs bit editing on a multi-bit pallet number while writing it into the VRAM, there are problems in that the load on the CPU becomes excessive and writing takes time.

That is, in the example of FIG.
When writing oo~b113) to VRAM3, first read 8 bits of data from address (000) of pallet 3, mask the 1st to 7th bits of them so that they are not rewritten, and write the 2nd bit b0. Rewrite only ゜ and write this to address (OOO). Next, Palette 3. of(
200) Read 8 bits of data from the address, mask the 1st to 7th bits so that they will not be rewritten, rewrite only the 0th bit) bob, and write this to (200).
Write to address. Thereafter, the reading of data, rewriting of only the O-th bit, and writing of the rewritten data are repeated until the last pallet 33.

As a result, as described above, the load on the CPU becomes excessive and writing takes a long time.

Means for Solving the Constituent Problems of the Invention The data processing circuit of the present invention consists of n bits (n
n types of m-bit parallel data groups are created by bundling m pieces (m is an integer of 2 or more) of n types of serial bit groups each occupying a specific bit position within a parallel data group of n types (where m is an integer of 2 or more). means for writing each of these n types of m-bit parallel data groups into n groups of storage areas having the same lower address, and having the same lower address within the n groups of storage areas. The device is equipped with means for reading n-bit parallel data from the same bit position within an area, and is configured to realize writing and reading of data into and from a VRAM or the like at high speed without depending on the CPU.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment FIG. 1 is a block diagram showing the configuration of a display storage device according to an embodiment of the data storage circuit of the present invention.

This display storage device consists of four serial/parallel conversion circuits 11
14, four latch circuits 21 to 24, a selector 30, a VRAM 40 composed of four memory planes 41 to 44, a write control circuit 50, and a read control circuit 6o.

The serial/parallel conversion circuit 11 generates a 4-bit pallet number group (bo. to bo3) and (bI. to b++) that appear sequentially on the four data signal lines S0 to S.

The 0th bit string (be., bl. rbZ. . . .) included in (bz.~b23)... is sequentially received, and as shown in the waveform diagram of FIG. 8-bit parallel data (bo., bIo, b2°・
...b. ). Similarly, the serial/parallel converter circuits 12 and 13 are also connected to pallet number groups (boo to b
o:+), (b+o~l)++), (bZ+1
~bZ:1)... The first bit string (bo
b, bz.

bz+'...), second bit b (oz, b
Iz, bzz'...), 3rd bit b03+ bI:
++ b23... are received sequentially, and each is synchronized with the clock signal Φ1 and converted into 8-bit parallel data (bob,
t)z, bz+...bye), (bo
x, b+□, b22...bqz).

(bO:l, ?)+3. bzs...bl,)
Convert to

The latch circuit 21 receives 8-bit parallel data (boo.

bIo, b2°...b7°) are latched in synchronization with the clock signal Φ2, and D is placed on the data line connected to the selector 30.
o. Bind and output. Similarly, the latch circuits 22 to 24 also receive 8-bit parallel data (bo+, b++,
bz+...b7u), (boz, b+z.

bzz“°bB), (boz, b++, btxo”
b'T3) are latched in synchronization with the clock signal Φ2 and placed on the data line connected to the selector 30.

Output as Dol Doff.

The write control circuit 50 selects the output of the launch circuit 21 by controlling the selector 30, and supplies the write address (000) to the memory brain 41, thereby converting the output D0° of the launch circuit 21 into write data d0°. and writes it to address (000) of the memory brain 41. Similarly, the write circuit 50 sequentially selects the outputs of the latch circuits 22, 23 and 24 by controlling the selector 30, and also controls the memory planes 42, 43.
and a write address (200) for each of 44,
(400), (600), the outputs D0. .

Write D, , D, as write data d01+dOX and doff at address (200) of the memory brain 42,
Write to address (400) of memory brain 43 and address (600) of memory brain 44, respectively.

In sequential reading for display, the read control circuit 60 reads data from the same bit position in the area having the same lower address (00), (01), (02), etc. in each memory plane 41 to 44. 4-bit pallet number group (be.+bO1+b0?+bos)
, (bIo, b++, b+z, ?)++)
, (bzo.

b tl, b zz, b zx) . . . are sequentially read out and supplied to a color lookup table (LUT).

Although the example of application to a display device using VRAM has been described above, the data processing circuit of the present invention can be applied to other appropriate devices such as a measuring device, an A/D conversion device, and a data filing device.

Effects of the Invention As explained in detail above, the data storage circuit of the present invention performs serial/parallel conversion processing on each serial bit group occupying a specific bit position within the parallel data group to create a parallel data group. means for writing each of these parallel data groups into a plurality of storage areas having the same lower address; and means for writing parallel data from the same bit position in an area having the same lower address in the storage areas of the plurality of groups; Since the structure includes a means for reading data, when applied to a display memory circuit, data can be written to and read from VRAM at high speed without depending on the CPU, and the load on the CPU is reduced. At the same time, the display speed is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment in which the data storage circuit of the present invention is applied to a display storage circuit, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, and FIG. 3 1 is a block diagram showing the configuration of a display storage circuit including a conventional VRAM; FIG. 11-14...Series/parallel conversion circuit, 21-24...
・Latch circuit, 30... Selector, 40... VRAM composed of memory brains 41 to 44, 50...
Write control circuit, 60... Read control circuit. Patent applicant: NEC Home Electronics Co., Ltd.

Claims (1)

[Claims] m pieces of each of n types of serial bit groups occupying a specific bit position within a parallel data group of n bits (n is an integer of 2 or more) that appear sequentially (m is an integer of 2 or more) means for creating n types of m-bit parallel data groups by bundling each data group; means for writing each of these n types of m-bit parallel data groups into n groups of storage areas having the same lower address; A data storage circuit comprising: means for reading n-bit parallel data from the same bit position in an area having the same lower address in n groups of storage areas.