JPS58142466A - Packing circut - Google Patents

Abstract

PURPOSE:To perform packing in a short time and to shorten data transfer time even when the volume of information is large by providing unit processing circuits corresponding to respective bits of the output of a data processing system. CONSTITUTION:Unit processing circuits P0-P15 are provided corresponding to respective bits of the output data OP of a data processing system and to comparing circuits 33 and selecting circuits 30 of those circuits P0-P15, a signal for showing the order of a word being inputted actually is inputted from a counter CC. Further, a selection signal SEL for specifying a pack bit is applied to the circuits 30 and shifters 32 and input data DI is applied to the circuits 30. The comparing circuits 33 compare the signal WN with the outputs of the shifters 32 and the results are latched in latch circuits 31 by the outputs of the circuits 30; and the outputs of the circuits 31 are outputted as output data DUn to shorten data transfer time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to buck circuits used in data processing systems.

In an image data processing system, when transferring data from an image memory that stores digital information related to an image to an external storage device via the main memory, the main objective is to shorten the transfer time. A round-back scheme may be used to reduce memory and external storage requirements.

FIG. 1 shows an example of an image data processing system. In the figure, 1 is a CPU (central processing unit), 2 is a CPU (central processing unit);
is a main memory having one-dimensional addresses, and the capacity per address is, for example, 16 bits. S is an external storage device such as MT (magnetic tape storage device) or DISK (magnetic disk storage device), and 4 is an image memory with two-dimensional addresses, and the capacity per address is the same as or smaller than main memory 2. , if you ask me, it's 1 bit. 5 is an image input device such as a drum scanner, and image data is inputted from the image input device 5 to the image memory 4. Image data in the image memory 4 is processed by an array processor 6 as necessary. The monitor 7 is used to monitor image data in the image memory 4.

When transferring image 1 data from the image memory 4 to the main memory 2, packing is performed in the memory-to-memory transfer module 8 because it operates with a 0PUI command. This is due to the following reason. Assume that the valid data in the image memory 4 is 1 bit.

If the data is transferred to main memory 2 as is, the data stored in main memory 2 will be 00...01 or 0.
0...00, only the lowest 1 bit has any meaning, and the upper 15 bits have no meaning.This wastes the storage capacity of main memory. It happens. The data in the image memory 4 is not sent to the main memory 2 as is, but is backed up in the transfer module 8 and then sent to the main memory 2.

In addition to packing data with 1 effective bit as described above, there are also cases where data is packed with 2 bits, 4 pits, and 8 bits, and there are also cases where all 16 bits are passed as valid data. .

FIGS. 2(a) to 2(e) show the relationship between data (input data) before being subjected to pack-through processing and data (output data) after being processed.

The same figure (a) shows the same figure (c) when performing 1-bit pack.
(e) shows the case where 2 pit backs are performed, (e) shows the case where 4 bit packs are performed, and (e) shows the case where 16 pit backs (through) are performed. 8 words, 4 words, 2 words, lower 1 bit of l word, 2 bits, 4 bits, 1
Six bits are arranged in order to form one new word.

Since there are various cases as described above, the transfer module needs to have a function of selectively packing according to specifications.

Implementation of the pack method has traditionally relied on software.

However, it has the disadvantage of long processing time, which is a particular problem when the amount of information is enormous, such as images.

An object of the present invention is to provide a packing circuit that can perform packing in a short time.

FIG. 3 shows an embodiment of a pack circuit according to the present invention. In the figure, P6 to P18 are unit processing circuits provided corresponding to each bit of the 16 output data DO. In addition, CC is a counter that is reset every time one word of input data is output, and by counting nine strobe pulses STR in synchronization with the input data, it is possible to check the circuit to which the word has been input, that is, the current number of the word. Generates a signal WM indicating whether or not is being input.

The unit processing circuits P0 to P15 are connected to the data lines shown in FIG. 4, respectively, for transmitting signals of each bit of input data. In the 41st line, A to P are symbols assigned in order from the data line that conveys the signal of the upper bit of the input data to the lower bit. Then, according to the output WH of the counter CC and the select signal SER specifying the number of packed pits, the bit signals transmitted through the selected one of the connected data lines are processed and output. .

FIG. 5 shows the (n+1)th (0≦n≦15) unit processing circuit Pn from the top, and is circled. In the figure, 30 is a selection circuit which selects one of the connected input data lines in accordance with the signal SEL when the signal WM reaches a predetermined setting value (described later).

31 is a latch circuit that receives the output of the 1 selection circuit,
When the latch pulse LP is applied, the output of the selection circuit 30 is latched.

32 is a shifter whose contents are shifted according to the number of packed bits, and it is set at which word input should be latched. As an example, the contents of the shifter 32 of the ninth unit processing circuit P6 from the highest order are shown in FIG. Figure 6 shows 16 bit back (through), 8
1st (0000), 2nd (0001), 8th (0010), and 6th (0100) for bit pack, 4 bit back, 8 pit pack, and 4 bit back, respectively.
), which means that the setting is such that latching is performed when the ninth (1000) data transfer is performed.

33 is a comparison circuit that compares the output (set value) of the shifter 32,
The output WN of the counter CC is compared, and when the two match, that is, when a predetermined number of words of data have been input, a latch pulse LP is generated. By this latch pulse LP, the latch circuit 31 latches the output of the selection circuit (30) as described above. bits (Fig. 2(a) to (e)
), that is, to select the data line that conveys the signal of that bit.

As an example, the overall operation of the back circuit when a 4-bit back command is specified is as follows. At the time of data transfer of the first words A6 to P8, the week selection circuit 30 of the upper four unit processing circuits P6 to P8
selects data lines M~P and reads the first read A8~P.
The lower 4 pits M0 to P6 of 9 are latched by the latch circuits 31 of the upper four unit processing circuits P6 to P8. During data transfer of the next word A1 to P1, the selection circuit 3 of the fifth to eighth unit processing circuits P4 to P7 from the higher order selects the data lines M to P, and the lower four pits M1 of the input word are selected. ~P1 is latched by the latch circuit 31 of the unit processing circuits P4 to P7. When transferring data of the 8th words A2 to P2, the 9th to 12th unit processing circuits P8 from the top
-P11 selection circuit 30 selects data lines M-P, and the lower 4 bits M2-P2 of the input word are latched by latch circuits 31 of unit processing circuits P6-P11. When transferring the data of the fourth word A3 to P3, the selection circuit 30 of the 13th to 16th unit processing circuits P12 to P15 from the higher order selects the data lines M to P, and selects the lower 4 bits of the input word. M3 to P3 are latched by the latch circuits 31 of the unit processing circuits P12 to P13. Thereafter, the data latched in the latch circuits 31 of all the unit processing circuits P6 to P15 is transferred as output data. This resets the counter CC. Thereafter, the same operation as above is repeated.

Even when the number of back bits is other than 4, backing is performed by the same operation as above.

Above we explained the case where one word is 16 bits,
The present invention can be similarly applied to cases where the number of bits in one word is other than 16.

According to the present invention, backing can be done in a short time,
Therefore, the time required for data transfer can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an image data processing system, FIGS. 2(a) to (e) are diagrams showing the correspondence of data before and after back processing, and FIG. 8 is a block diagram showing the back circuit of the present invention. A block diagram showing one embodiment, FIG. 4 is a diagram showing data lines to which unit processing circuits are connected, FIG. 5 is a block diagram showing the configuration of the unit processing circuit Pn, and FIG. 6 is a diagram showing the configuration of the unit processing circuit P5. It is a figure showing the contents of a shifter. CC... Counter, 30... Selection circuit, 31...
-Latch circuit, 32...shifter, 33...comparison circuit. Applicant Kiyoshi Inomata

Claims (1)

[Claims] Therefore, n
;&, data is input one word at a time. A back circuit that backs up these into a single word and outputs it, a counter that is reset each time one word of data is output and counts the number of times a word is input;
They are provided corresponding to each output bit, respectively, and when a predetermined same number of words are input according to the output of the counter,
a selection circuit that selects one bit of the currently input word in accordance with a signal specifying the number of back bits; a latch circuit that is provided corresponding to each output bit and receives the output of each selection circuit; a setting circuit provided corresponding to each number output bit and setting the predetermined number of times in response to a signal specifying the number of batter bits, and comparing a setting value of the setting circuit and a counted value of the counter; and a comparison circuit that provides a rounded latch pulse that causes the latch circuit to latch when the two match.