JPS6310449B2 - - Google Patents

Info

Publication number
JPS6310449B2
JPS6310449B2 JP12053182A JP12053182A JPS6310449B2 JP S6310449 B2 JPS6310449 B2 JP S6310449B2 JP 12053182 A JP12053182 A JP 12053182A JP 12053182 A JP12053182 A JP 12053182A JP S6310449 B2 JPS6310449 B2 JP S6310449B2
Authority
JP
Japan
Prior art keywords
data
memory
block
circuit
status signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP12053182A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5911443A (ja
Inventor
Toshio Yoshikawa
Kimihiro Ishitobi
Yamato Sato
Norya Murakami
Teruyoshi Takeuchi
Tomohisa Hirokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57120531A priority Critical patent/JPS5911443A/ja
Publication of JPS5911443A publication Critical patent/JPS5911443A/ja
Publication of JPS6310449B2 publication Critical patent/JPS6310449B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP57120531A 1982-07-13 1982-07-13 記憶制御回路 Granted JPS5911443A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57120531A JPS5911443A (ja) 1982-07-13 1982-07-13 記憶制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57120531A JPS5911443A (ja) 1982-07-13 1982-07-13 記憶制御回路

Publications (2)

Publication Number Publication Date
JPS5911443A JPS5911443A (ja) 1984-01-21
JPS6310449B2 true JPS6310449B2 (sv) 1988-03-07

Family

ID=14788576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57120531A Granted JPS5911443A (ja) 1982-07-13 1982-07-13 記憶制御回路

Country Status (1)

Country Link
JP (1) JPS5911443A (sv)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0820869B2 (ja) * 1987-02-06 1996-03-04 ヤマハ株式会社 電子楽器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51131228A (en) * 1975-04-25 1976-11-15 Philips Nv Device for processing digital information element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51131228A (en) * 1975-04-25 1976-11-15 Philips Nv Device for processing digital information element

Also Published As

Publication number Publication date
JPS5911443A (ja) 1984-01-21

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