JPS63104360A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63104360A JPS63104360A JP61250160A JP25016086A JPS63104360A JP S63104360 A JPS63104360 A JP S63104360A JP 61250160 A JP61250160 A JP 61250160A JP 25016086 A JP25016086 A JP 25016086A JP S63104360 A JPS63104360 A JP S63104360A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- heat
- semiconductor device
- transistor chip
- dielectric substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000000694 effects Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は高周波高出力用半導体装置に関し、特にその
放熱板の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a high-frequency, high-output semiconductor device, and particularly relates to an improvement of a heat sink thereof.
第４図は従来の半導体装置の構成を示す断面図であり、
図において、１ｄは放熱板、２ａは誘電体基板、３は該
誘電体基板２ａ上にパターニングされたメタライズ部、
４は誘電体基板２ａ上に搭載されたトランジスタチップ
、５は誘電体基板２ａ上に搭載されたＭＯＳキャパシタ
、６ａは接地部へ接続する接地ワイヤ、７ａ及び７ｂは
入力部へ接続する入力ワイヤ、８は入力リード、９は出
力リードである。FIG. 4 is a cross-sectional view showing the configuration of a conventional semiconductor device.
In the figure, 1d is a heat sink, 2a is a dielectric substrate, 3 is a metallized portion patterned on the dielectric substrate 2a,
4 is a transistor chip mounted on the dielectric substrate 2a, 5 is a MOS capacitor mounted on the dielectric substrate 2a, 6a is a ground wire connected to the ground section, 7a and 7b are input wires connected to the input section, 8 is an input lead, and 9 is an output lead.
従来の半導体装置では、入力リード８に入力される高周
波信号は入カワイヤ７ａ、ＭＯＳキャパシタ５、及び入
力ワイヤ７ｂを介してトランジスタチップ４のベース（
またはエミッタ）に導かれて増幅され、コレクタから出
力リード９を経て出力されるものであり、トランジスタ
チップ４のエミッタ（またはベース）は、接地ワイヤ６
ａにより誘電体基板２ａ面上のメタライズ部３を介して
放熱板１ｄに接地される。ここでトランジスタチップ４
で発生した熱は誘電体基板２ａおよび放熱板１ｄを介し
て半導体装置の取り付はケースへ伝導され、放熱される
。In the conventional semiconductor device, a high frequency signal inputted to the input lead 8 is transmitted to the base of the transistor chip 4 (
The emitter (or base) of the transistor chip 4 is connected to the ground wire 6.
A is grounded to the heat sink 1d via the metallized portion 3 on the surface of the dielectric substrate 2a. Here transistor chip 4
The heat generated is conducted to the case where the semiconductor device is mounted via the dielectric substrate 2a and the heat sink 1d, and is radiated.
従来の半導体装置は以上のように構成されているので、
全屈からなる放熱板が誘電体基板と同等に大きくなって
おり、重量が重くなるという問題点があった。Conventional semiconductor devices are configured as described above, so
There was a problem in that the fully bent heat sink was as large as the dielectric substrate, making it heavier.
この発明は上記のような問題点を解消するためになされ
たもので、放熱特性を従来の半導体装置と同程度にし、
かつ重量を軽減できる半導体装置を得ることを目的とす
る。This invention was made to solve the above problems, and has a heat dissipation characteristic comparable to that of conventional semiconductor devices.
Another object of the present invention is to obtain a semiconductor device whose weight can be reduced.
この発明に係る半導体装置は、放熱板の側面形状の一部
又は全部を末広がりのテーパ状あるいは階段状の形状と
したものである。In the semiconductor device according to the present invention, part or all of the side surface of the heat sink has a tapered shape or a stepped shape that widens toward the end.
この発明における半導体装置は、放熱板の側面形状を末
広がりのテーバ状あるいは階段状にすることによりトラ
ンジスタチップで発生した熱の流れに影響しない部分を
削除でき、装置の重量を軽減できる。In the semiconductor device according to the present invention, by making the side surface shape of the heat sink into a tapered shape that widens toward the end or a stepped shape, a portion that does not affect the flow of heat generated in the transistor chip can be eliminated, and the weight of the device can be reduced.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例による半導体装置を示し、
図において、１ａは放熱板、２は誘電体基板、３は誘電
体基板２上にパターニングされたメタライズ部、４は誘
電体基板２上に搭載されたトランジスタチップ、５は誘
電体基板２上に搭載されたＭＯＳキャパシタ、６ａは接
地部へ接続する接地ワイヤ、７ａ及び７ｂは入力部へ接
続する入力ワイヤ、８は入力リード、９は出力リードで
ある。FIG. 1 shows a semiconductor device according to an embodiment of the present invention,
In the figure, 1a is a heat dissipation plate, 2 is a dielectric substrate, 3 is a metallized portion patterned on the dielectric substrate 2, 4 is a transistor chip mounted on the dielectric substrate 2, and 5 is a metallized portion on the dielectric substrate 2. MOS capacitors are mounted, 6a is a ground wire connected to a grounding part, 7a and 7b are input wires connected to an input part, 8 is an input lead, and 9 is an output lead.
次に作用、効果について説明する。入力リード８に入力
される高周波信号は入カワイヤ７ａ、ＭＯＳキャパシタ
５及び入力ワイヤ７ｂを介してトランジスタチップ４の
ベース（またはエミッタ）に導かれて増幅され、コレク
タから出力リード９を経て出力されるものであり、トラ
ンジスタチップ４のエミッタ（又はベース）は接地ワイ
ヤ６ａにより誘電体基板２ａ面上のメタライズ部３を介
して放熱板１ａに接地される。ここで、トランジスタチ
ップ４で発生した熱はその下面と接触する誘電体基板２
ａの幅Ｗ１に伝わり、誘電体基板２ａ内では熱流拡がり
角度θ２で放熱板１ａとの接合面Ｗ２まで伝わる。次に
放熱板１ａ内では熱流 “拡がり角度θ３でケースへの
取り付は幅Ｗ３まで伝えられる。このように熱流を妨げ
ることなく放熱板を小さくできＭ量を軽減することが可
能となる。半導体装置の重量のほとんどは全屈放熱板が
占めるため、この発明の半導体装置と従来の半導体装置
との重量比は次のようになる。Next, the action and effect will be explained. The high frequency signal input to the input lead 8 is guided to the base (or emitter) of the transistor chip 4 via the input wire 7a, the MOS capacitor 5, and the input wire 7b, where it is amplified and output from the collector via the output lead 9. The emitter (or base) of the transistor chip 4 is grounded to the heat sink 1a via the metallized portion 3 on the surface of the dielectric substrate 2a by means of a ground wire 6a. Here, the heat generated in the transistor chip 4 is transferred to the dielectric substrate 2 which is in contact with the lower surface of the transistor chip 4.
The heat is transmitted to the width W1 of a, and within the dielectric substrate 2a, the heat flow is transmitted to the joint surface W2 with the heat sink 1a at a heat flow spread angle θ2. Next, within the heat sink 1a, the heat flow is transmitted to the case at the spreading angle θ3 up to the width W3.In this way, the heat sink can be made smaller without interfering with the heat flow, and the amount of M can be reduced.Semiconductor Since most of the weight of the device is occupied by the fully bent heat sink, the weight ratio between the semiconductor device of the present invention and the conventional semiconductor device is as follows.
従来の半導体装置の放熱板の断面積
（Ｗ２ ＋Ｗ３ ） ・ ｔ３／２（Ｗ２ ＋Ｗ
３ ） ／ ２
Ｗ２ ＝Ｗ１ ＋ ２ ｔ ２ ｔａｎ θ２Ｗ
３ ””Ｗ２ ＋ ２ ｔ ３ ｔａｎ θ３
−ＷＪ ＋ ２ ｔ ２ ｔａｎ θ２ ＋ ２
ｔ ３ ｔａｎ θ３より
（Ｗ＋＋２ｔ２ ｔａｎ θ２ ＋ Ｗ＋＋２ｔ２ ｔ
ａｎ θ２ ＋ ２ｔ３ ｔａｎ θ３）／２となる、
−例として、
Ｗｌ −１ｍｍ
ｔ２＝１ｍｍ
ｔ３＝１．５ｍｍ
θ２＝４５’
θ３＝４５’
Ｗ４ ＝ ｌ Ｑ ｍｍ
を考えると
なお、上記実施例では放熱板１ａの断面がテーパ状のも
のを示したが、これは階段形状にしても良い。Cross-sectional area of heat sink of conventional semiconductor device (W2 +W3) ・t3/2(W2 +W
3) / 2 W2 = W1 + 2 t 2 tan θ2W
3 ””W2 + 2 t 3 tan θ3
-WJ + 2 t 2 tan θ2 + 2
From t 3 tan θ3 (W++2t2 tan θ2 + W++2t2 t
an θ2 + 2t3 tan θ3)/2,
- As an example, considering Wl -1mm t2=1mm t3=1.5mm θ2=45'θ3=45' W4 = l Q mm It should be noted that in the above embodiment, the heat sink 1a has a tapered cross section. However, this may be made into a staircase shape.
また、誘電体基板２ａ；ｆ−補強するために第２図に示
すような放熱板１ｂを設けてもよく、また、誘電体基板
２ａを分割して第３図に示すような誘電体基Ｆｉｒａ、
２ｂ、２ｃとし、放熱板ＩＣを設けても上記実施例と同
様の効果を奏する。Furthermore, a heat dissipation plate 1b as shown in FIG. 2 may be provided for reinforcement of the dielectric substrate 2a; ,
2b and 2c, and a heat sink IC is provided, the same effect as in the above embodiment can be obtained.
以上のように、この発明に係る高周波高出力用半導体装
置によれば、放熱板のうちｌ・ランジスタチップで発生
した熱の流れに影響しない部分を削除するようにしたの
で、装置の重量を軽減できる効果がある。As described above, according to the high-frequency, high-output semiconductor device according to the present invention, since the portion of the heat sink that does not affect the flow of heat generated in the transistor chip is removed, the weight of the device is reduced. There is an effect that can be done.
第１図はこの発明の一実施例による半導体装置を示す断
面図、第２図および第３図はこの発明の他の実施例によ
る半導体装置を示す断面図、第４図は従来の半導体装置
を示す断面図である。
図において、ｌａｌ ｌｂ、ｌｅｔ ｌｄｌ は放
熱板、２ａ、２ｂ、２ｃは誘電体基板、３はメタライズ
部、４はトランジスタチップ、５はＭＯＳキャパシタ、
６ａ、６ｂは接地ワイヤ、７ａ、７ｂは入力ワイヤ、８
は入力リード、９は出力リード、１０は出力ワイヤであ
る。
なお、図中、同一符号は同−又は相当部分を示す。FIG. 1 is a sectional view showing a semiconductor device according to one embodiment of the present invention, FIGS. 2 and 3 are sectional views showing semiconductor devices according to other embodiments of the invention, and FIG. 4 is a sectional view showing a conventional semiconductor device. FIG. In the figure, lal lb, let ldl are heat sinks, 2a, 2b, 2c are dielectric substrates, 3 is a metallized part, 4 is a transistor chip, 5 is a MOS capacitor,
6a, 6b are ground wires, 7a, 7b are input wires, 8
9 is an input lead, 9 is an output lead, and 10 is an output wire. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (3)
れを放熱板上に搭載してなる高周波高出力用の半導体装
置において、 上記放熱板の側面形状の一部又は全部を末広がりのテー
パ状あるいは階段状の形状としたことを特徴とする半導
体装置。(1) In a high-frequency, high-output semiconductor device in which a transistor chip is placed on a dielectric substrate and this is mounted on a heat sink, part or all of the side surface shape of the heat sink is shaped into a tapered shape that widens toward the end. Alternatively, a semiconductor device characterized by having a step-like shape.
底辺を上辺とする等脚台形の斜辺の下方部分をその斜辺
とする等脚台形形状であることを特徴とする特許請求の
範囲第１項記載の半導体装置。(2) The side surface shape of the heat sink is an isosceles trapezoid whose oblique side is the lower part of the oblique side of the isosceles trapezoid whose upper side is the base of the transistor chip. The semiconductor device described.
底辺を上辺とする等脚台形の斜辺の下方部をその斜辺と
する等脚台形の斜辺を階段状とした形状であることを特
徴とする特許請求の範囲第１項記載の半導体装置。(3) The side surface shape of the heat sink is characterized in that the oblique side of the isosceles trapezoid whose upper side is the base of the transistor chip is a step-like shape, and the oblique side is the lower part of the oblique side of the isosceles trapezoid whose upper side is the bottom side of the transistor chip. A semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61250160A JPS63104360A (en) | 1986-10-20 | 1986-10-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61250160A JPS63104360A (en) | 1986-10-20 | 1986-10-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63104360A true JPS63104360A (en) | 1988-05-09 |
Family
ID=17203711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61250160A Pending JPS63104360A (en) | 1986-10-20 | 1986-10-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63104360A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0384301A2 (en) * | 1989-02-17 | 1990-08-29 | Nokia Mobile Phones Ltd. | Cooling arrangement for a transistor |
| EP0603928A1 (en) * | 1992-12-21 | 1994-06-29 | Delco Electronics Corporation | Hybrid circuit |
| JPWO2008078788A1 (en) * | 2006-12-26 | 2010-04-30 | 京セラ株式会社 | Heat dissipation board and electronic device using the same |
-
1986
- 1986-10-20 JP JP61250160A patent/JPS63104360A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0384301A2 (en) * | 1989-02-17 | 1990-08-29 | Nokia Mobile Phones Ltd. | Cooling arrangement for a transistor |
| US5214309A (en) * | 1989-02-17 | 1993-05-25 | Nokia Mobile Phones Ltd. | Thermally conductive bar cooling arrangement for a transistor |
| EP0603928A1 (en) * | 1992-12-21 | 1994-06-29 | Delco Electronics Corporation | Hybrid circuit |
| JPWO2008078788A1 (en) * | 2006-12-26 | 2010-04-30 | 京セラ株式会社 | Heat dissipation board and electronic device using the same |
| JP5202333B2 (en) * | 2006-12-26 | 2013-06-05 | 京セラ株式会社 | Heat dissipation board and electronic device using the same |
| EP2109138B1 (en) * | 2006-12-26 | 2015-12-23 | Kyocera Corporation | Heat dissipating substrate and electronic device using the same |
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