JPS63104345A - Method for measuring semiconductor device - Google Patents
Method for measuring semiconductor deviceInfo
- Publication number
- JPS63104345A JPS63104345A JP25100986A JP25100986A JPS63104345A JP S63104345 A JPS63104345 A JP S63104345A JP 25100986 A JP25100986 A JP 25100986A JP 25100986 A JP25100986 A JP 25100986A JP S63104345 A JPS63104345 A JP S63104345A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- measuring
- mosfet
- semiconductor device
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 title claims description 10
- 230000015556 catabolic process Effects 0.000 claims abstract description 14
- 230000000694 effects Effects 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 2
- 230000005684 electric field Effects 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000008188 pellet Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 238000010338 mechanical breakdown Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の測定方法に関し、特に絶縁ゲート
型電界効果トランジスタ(以下MOsFETと呼ぶ)を
有する半導体装置の静電破壊耐量の測定方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for measuring semiconductor devices, and particularly to a method for measuring electrostatic breakdown strength of a semiconductor device having an insulated gate field effect transistor (hereinafter referred to as MOsFET). .
従来この種の半導体装置の静電破壊耐量の測定方法とし
ては、第2図の回路図に示す様なCチャージテストが知
られている。すなわち、第2図においてコンデンサ21
を電圧■に充電しその充電したエネルギーを被測定素子
22の端子に印加し素子の破壊の有無を調べるのである
。この場合印加したエネルギーはE = (−CV”で
表わされる。ここでC:コンデンサ21の容量V:充電
した電圧である。Conventionally, a C charge test as shown in the circuit diagram of FIG. 2 has been known as a method for measuring the electrostatic breakdown strength of this type of semiconductor device. That is, in FIG.
The charged energy is applied to the terminals of the device under test 22 to check whether the device is damaged or not. In this case, the applied energy is expressed as E = (-CV), where C: capacitance of the capacitor 21, V: charged voltage.
一般にMOSFETは静電破壊に弱い半導体装置と云わ
れている。特に素子の性能を高めるためゲート酸化膜は
より薄く設計される傾向にある。一方MOS構造におけ
る絶縁耐圧BYはゲート酸化膜厚toxとBV=に*j
oxの関係にある。(Kは比例定数。)従って静電破壊
耐量は低下する方向である。このようなMOSFETに
おいてはその製造プロセス上の条件のバラツキが原因と
なって静電破壊耐量の劣小素子は、製造工程中のチェッ
クで除去しなければならない。しかしながら上述した従
来の測定方法では素子の静電破壊耐量を正確に知るには
、その素子を破壊させるまでサージエネルギーを印加し
なければならず全数の素子を測定する場合には適用でき
なかった。又破壊させないで測定する場合は素子にサー
ジエネルギーを印加することがその素子の特性を劣化せ
しめる危険性を伴なうので破壊するエネルギーより充分
低いエネルギー印加にとどめていたのでその確度は非常
に低いという欠点があった。Generally, MOSFETs are said to be semiconductor devices that are susceptible to electrostatic discharge damage. In particular, gate oxide films tend to be designed thinner to improve device performance. On the other hand, the dielectric breakdown voltage BY in the MOS structure is determined by the gate oxide film thickness tox and BV=*j
There is an ox relationship. (K is a proportionality constant.) Therefore, the electrostatic breakdown resistance tends to decrease. In such MOSFETs, elements with poor electrostatic breakdown resistance due to variations in manufacturing process conditions must be removed by checking during the manufacturing process. However, in order to accurately determine the electrostatic breakdown capacity of an element with the conventional measurement method described above, surge energy must be applied until the element is destroyed, and it cannot be applied when measuring all the elements. In addition, when measuring without destroying the element, applying surge energy to the element carries the risk of degrading the characteristics of the element, so the application of energy was kept sufficiently lower than the energy that would destroy it, so the accuracy was very low. There was a drawback.
本発明の静電破壊耐量の測定方法は、半導体装置の同一
ペレットに設けたチェック素子の絶縁耐圧を測定するこ
とによ、9M08FETの静電破壊耐量を測定するので
ある。The method for measuring electrostatic breakdown strength of the present invention measures the electrostatic breakdown strength of a 9M08FET by measuring the dielectric strength of a check element provided on the same pellet of a semiconductor device.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の測定方法の概念図である。1はMOS
B”ET 2はチェック素子である。FIG. 1 is a conceptual diagram of the measuring method of the present invention. 1 is MOS
B"ET 2 is a check element.
第3図は第1図のチェック素子2のA −A’間の縦断
面図である。P型Si基板31に高濃度のP型拡散層3
2を設けしかる後にMOSFETのゲート酸化膜を形成
する工程で同時には化膜33を形成しP型拡散層32を
開孔しアルミ電極34・35を形成する。このようなチ
ェック素子の酸化膜3:3はMOS1i’ETのゲート
酸化膜の全く同等の膜厚、膜質を有し、アルミ電極34
・35の間に電圧を印加しチェック素子が破壊する電圧
を測定することによfiMOSFETの静電破壊耐量の
推定が確度良く出来る。第4図にチェック素子の絶縁耐
圧BVとMOSFETの静電破壊1−HEESDの相関
例を示す。FIG. 3 is a longitudinal sectional view taken along line A-A' of the check element 2 shown in FIG. High concentration P type diffusion layer 3 on P type Si substrate 31
After forming the gate oxide film 2, a oxide film 33 is formed at the same time as the gate oxide film of the MOSFET, holes are opened in the P-type diffusion layer 32, and aluminum electrodes 34 and 35 are formed. The oxide film 3:3 of such a check element has exactly the same thickness and film quality as the gate oxide film of the MOS1i'ET, and has the same thickness and quality as the gate oxide film of the MOS1i'ET, and
- By applying a voltage between 35 and measuring the voltage at which the check element breaks down, the electrostatic breakdown capacity of the fiMOSFET can be estimated with high accuracy. FIG. 4 shows an example of the correlation between the dielectric breakdown voltage BV of the check element and the electrostatic breakdown 1-HEESD of the MOSFET.
以上説明したように本発明は、MOSF’ETのゲート
酸化膜と同一工程で形成し、全く膜厚膜質の酸化膜を用
い1ヒM08g造のチェック素子の絶縁耐圧を測定する
ことによりご〜tO8F”ETをvL壊したり特性劣化
を起こせしめずにMOSFETの静・メイ破壊耐量のチ
ェックができる効果がある。As explained above, the present invention has been developed by measuring the dielectric strength voltage of a check element made of 1-6M08G using an oxide film formed in the same process as the gate oxide film of MOSF'ET and having a very thick film quality. ``It has the effect of being able to check the static and mechanical breakdown resistance of a MOSFET without damaging the VL or causing characteristic deterioration of the ET.
第1図は本発明の半導体装置の測定方法の概念図。
1・・・・・・MOSFET、2・・・・・・チェック
素子第2図は従来の半導体装置の測定方法。
21・・・・・・コンデンサ、22・・・・・・被測定
素子第3図は第1図A−A線縦断面図。
31・・・・・・PiSi基板、32・・・・・・高濃
度P型拡散層、33・・・・・・酸化膜、34.35・
・・・・・アルミ電極
第4図チェック素子の絶縁耐圧BVとMOSFETの静
電破壊耐量エネルギーEEsDの相関例。
′斥、;
代理人 弁理士 内 原 召・1・、 ハ第
2 ■FIG. 1 is a conceptual diagram of a method for measuring a semiconductor device according to the present invention. 1...MOSFET, 2...Check element Figure 2 shows a conventional method for measuring semiconductor devices. 21... Capacitor, 22... Element to be measured. FIG. 3 is a vertical sectional view taken along the line A-A in FIG. 31... PiSi substrate, 32... High concentration P type diffusion layer, 33... Oxide film, 34.35.
...Aluminum electrode Fig. 4 Example of correlation between dielectric strength voltage BV of check element and electrostatic breakdown energy EEsD of MOSFET. ′斥、; Agent: Patent Attorney Uchihara Sho. 1.、Ha No.
2 ■
Claims (1)
ト酸化膜と同一工程で形成された酸化膜をもつMOS構
造のチェック素子を形成し、該チェック素子の絶縁耐圧
を測定することにより前記絶縁ゲート型電界効果トラン
ジスタの静電破壊耐量を測定することを特徴とする半導
体装置の測定方法。By forming a MOS structure check element having an insulated gate field effect transistor and having an oxide film formed in the same process as the gate oxide film, and measuring the dielectric strength voltage of the check element, the insulated gate electric field can be measured. A method for measuring a semiconductor device, characterized by measuring the electrostatic breakdown resistance of an effect transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25100986A JPS63104345A (en) | 1986-10-21 | 1986-10-21 | Method for measuring semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25100986A JPS63104345A (en) | 1986-10-21 | 1986-10-21 | Method for measuring semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63104345A true JPS63104345A (en) | 1988-05-09 |
Family
ID=17216281
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25100986A Pending JPS63104345A (en) | 1986-10-21 | 1986-10-21 | Method for measuring semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63104345A (en) |
-
1986
- 1986-10-21 JP JP25100986A patent/JPS63104345A/en active Pending
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