JPS61190982A - Preventive circuit for electrostatic breakdown - Google Patents
Preventive circuit for electrostatic breakdownInfo
- Publication number
- JPS61190982A JPS61190982A JP3034185A JP3034185A JPS61190982A JP S61190982 A JPS61190982 A JP S61190982A JP 3034185 A JP3034185 A JP 3034185A JP 3034185 A JP3034185 A JP 3034185A JP S61190982 A JPS61190982 A JP S61190982A
- Authority
- JP
- Japan
- Prior art keywords
- electrostatic breakdown
- gate
- electrostatic
- static electricity
- fuse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015556 catabolic process Effects 0.000 title claims abstract description 20
- 230000003449 preventive effect Effects 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000005259 measurement Methods 0.000 claims abstract description 11
- 230000002265 prevention Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 16
- 230000005611 electricity Effects 0.000 abstract description 13
- 230000003068 static effect Effects 0.000 abstract description 13
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は静電破壊防止技術、特に、ＭＯＳ ＦＥＴにお
けるゲートの静電破壊を防止するのに適用して有効な技
術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique for preventing electrostatic discharge damage, and particularly to a technique that is effective when applied to prevent electrostatic discharge breakdown of a gate in a MOS FET.
ＭＯＳ ＦＥＴよりなる半導体素子において、いわゆる
ＴＥＧ（Ｔｅｓｔ Ｅｌｅｍｅｎｔ Ｇｒｏｕｐ）によ
りスレッシュホールド電圧（Ｖ ｔｈ）を測定する場合
、ｖｔｈ測定用のバットにプローブを接触させてｖｔｈ
測定器により測定することが行われる。When measuring the threshold voltage (V th) of a semiconductor device consisting of a MOS FET using a so-called TEG (Test Element Group), the probe is brought into contact with the butt for vth measurement.
Measurement is performed using a measuring device.
ところが、この種の半導体素子の製造過程における前工
程プロセスで誘起される静電気により、ＭＯＳ ＦＥＴ
のゲートの静電破壊が生じるため、ｖｔｈの測定が不能
となる場合があることが本発明者によって見い出された
。However, due to static electricity induced in the front-end process in the manufacturing process of this type of semiconductor device, the MOS FET
The inventors have found that measurement of vth may become impossible due to electrostatic breakdown of the gate.
なお、ウエハブローバについては、株式会社工業調査会
、昭和５７年１１月１５日発行、「電子材料Ｊ １９Ｂ
３年別冊、Ｐ１９５〜Ｐ１９８に記載されている。Regarding wafer blowers, please refer to "Electronic Materials J 19B" published by Industrial Research Institute Co., Ltd., November 15, 1981.
It is described in the 3rd year special issue, pages 195 to 198.
本発明の目的は、半導体素子の静電破壊を防止すること
のできる技術を提供することにある。An object of the present invention is to provide a technique that can prevent electrostatic damage to semiconductor devices.
本発明の他の目的は、前工程プロセスによって誘起され
るＭＯＳ ＦＥＴのゲートの静電破壊を防止することの
できる技術を提供することにある。Another object of the present invention is to provide a technique that can prevent electrostatic damage to the gate of a MOS FET caused by a pre-process.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
零順において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in Zero Jun is as follows.
すなわち、半導体素子の静電破壊を防止すべき部分にヒ
ユーズ回路を組み込むことにより、このヒユーズ回路を
通して静電気を放電させることができ、ＭＯＳ ＦＥＴ
のゲートの如き部分の静電破壊を防止することができる
ものである。In other words, by incorporating a fuse circuit in the part of the semiconductor element where electrostatic damage should be prevented, static electricity can be discharged through this fuse circuit, and the MOS FET
This can prevent electrostatic damage to parts such as gates.
第１図は本発明による一実施例である静電破壊防止回路
の概略図である。FIG. 1 is a schematic diagram of an electrostatic breakdown prevention circuit according to an embodiment of the present invention.
本実施例においては、半導体素子の一例としてのＭＯＳ
ＦＥＴに本発明を適用したものであり、このＭＯＳ
ＦＥＴ Ｉは半導体基板（ウェハ）Ｗ上に前工程プロセ
スで形成されている。このようなＭＯＳ ＦＥＴ１では
、そのゲート２において静電破壊が起こり、ＳｉＯ□膜
よりなるゲート酸化膜が絶縁破壊されるので、本実施例
はこのＭＯＳ ＦＥＴ １のゲート２における静電破壊
を防止するものである。In this embodiment, a MOS as an example of a semiconductor element is used.
The present invention is applied to FET, and this MOS
The FET I is formed on a semiconductor substrate (wafer) W in a pre-process. In such a MOS FET 1, electrostatic breakdown occurs at the gate 2, and the gate oxide film made of the SiO□ film is dielectrically broken down, so this embodiment prevents electrostatic breakdown at the gate 2 of the MOS FET 1. It is something.
前記ＭＯ５ＦＥＴ １のソース、ドレインはパットＡ
。The source and drain of MO5FET 1 are pad A.
.
Ｂに配線され、またＭＯＳ ＦＥＴ １のゲート２はク
ランプダイオード３に配線接続されている。The gate 2 of the MOS FET 1 is connected to the clamp diode 3 by wiring.
本実施例では、前記のゲート破壊を防止するためのヒユ
ーズ回路４が設けられているものである。In this embodiment, a fuse circuit 4 is provided to prevent the aforementioned gate breakdown.
このヒユーズ回路４は、ＭＯＳ ＦＥＴ １のゲート２
に配線されたパットＣおよびクランプダイオード３に配
線されたパットＤと、両パフトＣとＤとの間に形成され
たヒユーズ５とからなる。This fuse circuit 4 connects the gate 2 of MOS FET 1.
The pad C is wired to the pad C, the pad D is wired to the clamp diode 3, and the fuse 5 is formed between the pads C and D.
ヒユーズ５はウェハの前工程プロセスにおける比較的初
期にヒユーズプロセスで形成することができる。The fuse 5 can be formed by a fuse process relatively early in the wafer pre-process.
次に、本実施例の作用について説明する。Next, the operation of this embodiment will be explained.
ウェハＷへの前工程プロセスを実施する過程において静
電気が誘起され、その静電荷が回路内にチャージアップ
される。この静電気はＴＥＧによるｖｔｈ測定時にＭＯ
Ｓ ＦＥＴ １のゲート２の静電破壊を起こし、ｖｔｈ
の測定不能をひき起こす結果となる。Static electricity is induced in the process of performing a pre-process on the wafer W, and the static electricity is charged up in the circuit. This static electricity is removed from MO when measuring vth by TEG.
Electrostatic damage to gate 2 of S FET 1 occurs, causing vth
This results in the inability to measure.
そこで、このようなりｔｈの測定不能をひき起こすゲー
ト２の静電破壊を防止するため、本実施例ではヒユーズ
回路４がウェハ上に作り込まれ、ゲート２およびクラン
プダイオード３と接続されている。Therefore, in order to prevent electrostatic discharge damage to the gate 2 that would cause such an inability to measure th, in this embodiment, a fuse circuit 4 is fabricated on the wafer and connected to the gate 2 and the clamp diode 3.
したがって、発生した静電気はこのヒユーズ回路４を通
して放電されることになり、静電気のチャージアップに
起因する静電破壊を未然に確実に防止することができる
。Therefore, the generated static electricity is discharged through the fuse circuit 4, and electrostatic damage caused by static electricity charge-up can be reliably prevented.
このヒユーズ回路４のヒユーズ５はＭＯＳ ＦＥＴ １
の動作時においてｖｔｈ測定器（図示せず）でｖｔｈの
測定を行う直前に電気的または機械的に切断さ° れる
。ヒユーズ５の切断方法としては、電圧印加手段（図示
せず）を使用し、その端子をパットＣとＤに当ててヒユ
ーズ４の切断に十分な電圧を印加することが考えられる
。この電圧印加手段としては、特別なものを使用しても
よいが、ｖｔｈ測定器の測定端子を測定の直前にパラｌ
−Ｃ，Ｄに当ててヒユーズ４を切断すれば、測定と同時
的に一つの手段でヒユーズ切断もできるので、極めて便
利である。Fuse 5 of this fuse circuit 4 is MOS FET 1
During operation, the VTH measuring device (not shown) is electrically or mechanically disconnected just before measuring VTH. One possible way to cut the fuse 5 is to use a voltage applying means (not shown) and apply a voltage sufficient to cut the fuse 4 by applying its terminals to the pads C and D. A special voltage applying means may be used, but the measurement terminal of the VTH measuring device must be connected to the parallax immediately before measurement.
-C and D to cut the fuse 4, it is extremely convenient because the fuse can be cut by one means at the same time as the measurement.
（１）、静電破壊を防止すべき部分にヒユーズ回路を組
み込むことにより、このヒユーズ回路を通して静電気を
放電できるので、半導体素子の静電破壊を防止できる。(1) By incorporating a fuse circuit in a portion where electrostatic damage should be prevented, static electricity can be discharged through the fuse circuit, thereby preventing electrostatic damage to semiconductor elements.
（２）、半導体素子がＭＯＳ ＦＥＴであることにより
、前工程プロセスによって誘起されるＭＯＳ ＦＥＴの
ゲートの静電破壊を防止できる。(2) Since the semiconductor element is a MOS FET, it is possible to prevent electrostatic breakdown of the gate of the MOS FET induced by the previous process.
（３）、ヒユーズ回路の切断をｖｔｈ測定手段で行うこ
とにより、測定と同時的に１つの手段でヒユーズ切断を
行うことができ、極めて便利である。(3) By cutting the fuse circuit using the vth measuring means, the fuse can be cut simultaneously with the measurement using one means, which is extremely convenient.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.
たとえば、ヒユーズの形成時や切断手段等としては前記
以外の様々なものとすることができる。For example, various methods other than those described above may be used when forming the fuse or as a cutting means.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるＭＯＳＦＥＴのゲー
トの静電破壊防止に適用した場合について説明したが、
それに限定されるものではなく、たとえば、バイポーラ
ＩＣ等にも広く適用できる。In the above explanation, we have mainly explained the case where the invention made by the present inventor is applied to the prevention of electrostatic damage of the gate of MOSFET, which is the field of application that formed the background of the invention.
The present invention is not limited thereto, and can be widely applied to bipolar ICs, etc., for example.
また、前工程プロセスで誘起される静電気に起因するゲ
ート静電破壊を起こす可能性のある半導体素子に適用で
き、特に、ゲート酸化膜が極めて薄く、静電破壊を起こ
し易い半導体素子や、プロセスにより決定されるクラン
プダイオードの接合耐圧以上のｖｔｈ値を持つＭＯＳが
含まれる半導体素子にも通用できる。In addition, it can be applied to semiconductor devices that may cause gate electrostatic breakdown due to static electricity induced in pre-processing processes, and is particularly applicable to semiconductor devices with extremely thin gate oxide films that are prone to electrostatic breakdown, and It can also be applied to a semiconductor device including a MOS having a vth value higher than the determined junction breakdown voltage of the clamp diode.
第１図は本発明による一実施例である静電破壊防止回路
の概略説明図である。
１・・・ＭＯＳＦＥＴ（半導体素子）、２・・・ゲート
、３・・・クランプダイオード、４・・・ヒユーズ回路
、５・・・ヒユーズ。
第 １ 図FIG. 1 is a schematic explanatory diagram of an electrostatic breakdown prevention circuit according to an embodiment of the present invention. 1... MOSFET (semiconductor element), 2... Gate, 3... Clamp diode, 4... Fuse circuit, 5... Fuse. Figure 1
Claims (1)
を防止すべき部分にヒューズ回路を組み込んでなること
を特徴とする静電破壊防止回路。 ２、半導体素子がＭＯＳＦＥＴであり、ヒューズ回路が
ＭＯＳＦＥＴのゲート電極とクランプダイオードとの間
に設けられていることを特徴とする特許請求の範囲第１
項記載の静電破壊防止回路。 ３、ヒューズ回路がＭＯＳＦＥＴの動作時に電圧を印加
することにより切断されることを特徴とする特許請求の
範囲第２項記載の静電破壊防止回路。 ４、ヒューズ回路の切断が測定端子による電圧の印加に
より行われることを特徴とする特許請求の範囲第３項記
載の静電破壊防止回路。[Scope of Claims] 1. An electrostatic breakdown prevention circuit for a semiconductor device, which is characterized by incorporating a fuse circuit in a portion where electrostatic breakdown is to be prevented. 2. Claim 1, characterized in that the semiconductor element is a MOSFET, and the fuse circuit is provided between the gate electrode of the MOSFET and the clamp diode.
Electrostatic damage prevention circuit described in Section 1. 3. The electrostatic damage prevention circuit according to claim 2, wherein the fuse circuit is disconnected by applying a voltage during operation of the MOSFET. 4. The electrostatic breakdown prevention circuit according to claim 3, wherein the fuse circuit is disconnected by applying a voltage through a measurement terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3034185A JPS61190982A (en) | 1985-02-20 | 1985-02-20 | Preventive circuit for electrostatic breakdown |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3034185A JPS61190982A (en) | 1985-02-20 | 1985-02-20 | Preventive circuit for electrostatic breakdown |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61190982A true JPS61190982A (en) | 1986-08-25 |
Family
ID=12301126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3034185A Pending JPS61190982A (en) | 1985-02-20 | 1985-02-20 | Preventive circuit for electrostatic breakdown |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61190982A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04158578A (en) * | 1990-10-22 | 1992-06-01 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
-
1985
- 1985-02-20 JP JP3034185A patent/JPS61190982A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04158578A (en) * | 1990-10-22 | 1992-06-01 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
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