JPH0237764A - Mos type semiconductor device - Google Patents

Abstract

PURPOSE:To automate and simplify a measuring operation and to enhance its efficiency by a method wherein a measuring terminal used to check the dielectric breakdown strength of a gate oxide film is installed in the same arrangement region as an external-lead extraction terminal. CONSTITUTION:Many pieces of external-lead extraction terminals 12 are arranged in a peripheral part of a chip 11 ; a peripheral circuit 13 connected to the external-lead extraction terminals is arranged and installed at their inside; in addition, an internal circuit 14 is arranged and installed at its inside. A measuring terminal 15 used to check the dielectric breakdown strength of a gate oxide film is arranged and installed in one part of a peripheral region, of the chip 11, where the external-lead extraction terminals 12 are arranged. During an inspection process of a semiconductor wafer, a probe of a multiprobe characteristic measuring apparatus is arranged so as to come into contact with the measuring terminal 15 formed in advance on the chip 11; a program for dielectric breakdown strength measuring use is prepared before an inspection operation; the dielectric breakdown strength of the gate oxide film can be measured. Thereby, a measuring operation can be automated and simplified while its efficiency can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type semiconductor device, and more particularly to an MO3 type semiconductor device having a gate oxide dielectric strength measurement terminal.

[Conventional technology]

One of the manufacturing processes for MO3 type semiconductor devices is the step of forming a gate oxide film, but due to charge accumulation during the subsequent ion implantation and etching steps, electrostatic breakdown of the gate oxide film often occurs, resulting in defective semiconductor devices. It has become.

A semiconductor device for evaluating electrostatic breakdown of the gate oxide film due to charge accumulation is fabricated in the slit shell, and one example thereof is shown in FIG.

A field oxide film 20 and a gate acid 1 are formed on a semiconductor substrate 10.
It is formed by forming a filler film 30, then forming an electrode made of a conductive polycrystalline silicon layer 40 on the gate oxide film 30, and further providing an insulating film 50 and patterning it. A voltage is applied between the electrode made of the conductive polycrystalline silicon layer 40 and the semiconductor substrate 51 to form a gate oxide film 53.
We measure the dielectric strength of the product and evaluate electrostatic damage.

Conventionally, in a general MO3 type semiconductor device, a dummy element for evaluating the gate oxide film electrostatic damage described above is formed separately from the original element in the device, as shown in Figure 3, and the dummy element is formed separately from the original element in the device when necessary. Electrostatic damage evaluation is performed using dummy elements. Or as shown in FIG. 4, a semiconductor wafer 47
A dummy element 45 is placed on top of the MOS type semiconductor element (chip) 4.
It may be formed at a location different from 1.

In recent years, as MOS semiconductor devices have become more highly integrated, gate oxide films have also become thinner, making it easier for electrostatic damage to occur due to charge accumulation.If the gate oxide film is further destroyed by charge accumulation, the semiconductor In the wafer inspection process, the semiconductor chip becomes defective, but if the gate oxide film is not completely destroyed and the film quality changes, making it easier for leakage current to flow, the semiconductor chip becomes a good product in the semiconductor wafer inspection process and passes through the subsequent process. Therefore, measuring the dielectric strength of the gate oxide film is becoming increasingly essential.

rProblems to be Solved by the Invention] In the conventional MOS type semiconductor device described above, when a dummy element for evaluating gate oxide film electrostatic damage is formed in the MOS type semiconductor device, it is separated from the external lead extraction terminal. , and its dimensions are relatively small. Therefore, in order to measure the dielectric strength, it is necessary for an operator to measure each chip using a withstand voltage measuring device. Moreover, since the measurement terminal of the dummy element is small, It is difficult to make contact with the measuring needle. This is exactly the same even when the dummy element is formed on another chip outside the MOS type semiconductor device. Therefore, when measuring the dielectric strength of each semiconductor wafer or chip that constitutes a MOS type semiconductor device,
All of this must be done manually by the operator, and there are problems in that the measurement requires a large amount of man-hours and the measurement efficiency is poor. In addition, if the dummy element is formed at a different location from the MOS type semiconductor device, in addition to the above problems, the M
There is a problem in that it is not possible to know the gate oxide film dielectric strength voltage for each chip of an O3 type semiconductor device.

[Means to solve the problem]

The MOS type semiconductor device of the present invention has a dummy element having a MOS structure for checking a gate oxide film dielectric strength voltage in a part of the chip, and a measurement terminal which is the gate electrode of the dummy element. are provided in the same array area as the external lead extraction terminals arrayed on the chip.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout diagram of a nap 11 of a MOS type semiconductor device showing an embodiment of the present invention.A large number of external lead extraction terminals 12 made of aluminum film are arranged around the periphery of the chip 11. Peripheral circuits 13 such as input/output buffers connected to these external read output terminals 12 are provided inside, and internal circuits 14 such as memory cells and arithmetic circuits are provided further inside.

The measurement terminal 15 for checking the gate oxide film insulation withstand voltage is connected to the chip 11 on which the external lead extraction terminals 12 are arranged.
The structure is shown in FIG. 5. In this embodiment, the measurement terminal 15 has the same size as the external lead extraction terminal 12 and is arranged in the same arrangement area as these terminals.

Therefore, in a MOS semiconductor device having a chip with such a configuration, the probe of a multi-probe characteristic measuring device conventionally used in the semiconductor wafer inspection process is attached to the measurement terminal 15 formed in advance on the chip 11. By arranging them so that they are in contact with each other, and by preparing a program for the multi-probe characteristic measuring device to measure the dielectric strength voltage prior to the actual inspection, it is possible to measure the dielectric strength voltage of the gate oxide film as part of the inspection process. Measurement becomes possible.

Therefore, it is possible to automate the measurement of the gate oxide film dielectric strength voltage, which eliminates the need for manual measurement by operators, thereby reducing the number of man-hours and improving measurement efficiency. Here, the measurement terminal 15 may be configured to also serve as a part of the external lead extraction terminal 12 if it does not have an electrical influence on other circuits.

Furthermore, the size of the measurement terminal 15 does not necessarily have to be the same as the external lead extraction terminal 12, and it is possible to make it smaller or larger as long as it does not become too small. Actually at least 5 of the external lead extraction terminals
It is preferable to have an area of 0%.

FIG. 2 is a layout diagram of an MO3 type semiconductor chip 21 showing a second embodiment of the present invention.

The difference from the first embodiment is that a conductive polycrystalline silicon layer 26 connected to a measurement terminal 15 for checking the gate oxide film dielectric strength voltage is arranged to surround the periphery of the semiconductor chip 21. This is because the larger the area of the conductive polycrystalline silicon layer that directly receives charges compared to the area of the gate oxide film due to charge accumulation, the easier it is to detect electrostatic damage caused by charges MFII.

Further, the conductive polycrystalline silicon layer 26 may be placed anywhere as long as it does not affect the operation of the semiconductor chip 21, and its shape can be freely set.

〔Effect of the invention〕

As explained above, in the present invention, by providing the measurement terminal for checking the gate oxide film dielectric strength voltage in the same array area as the external lead extraction terminal, the size of the measurement terminal can be made almost the same as that of the external lead extraction terminal. It becomes possible to measure the membrane dielectric strength voltage for each chip using a conventional multi-probe characteristic device, which has the effect of achieving automation of the measurement, simplifying the measurement, and improving the efficiency of the measurement.

Furthermore, in the semiconductor wafer inspection process using a multi-probe characteristic device, if the allowable value of the gate oxide film dielectric strength is determined and an inker dot is placed on defective products, the gate oxide film will not be completely destroyed due to charge accumulation. Even if the quality of the oxide film changes and leakage current is more likely to flow, the semiconductor wafer inspection process will not incorrectly judge the product as good, unlike in the past, so chips with poor gate oxide dielectric breakdown voltage will not be detected until the semiconductor chip inspection process. This also has the effect of eliminating the need for wasted man-hours, as no messages are sent.

[Brief explanation of the drawing]

1 and 2 are layout diagrams of a MOS type semiconductor device showing a first embodiment and a second embodiment of the present invention, respectively, and FIGS. 3 and 4 show the first and second conventional examples, respectively. FIG. 5 is a sectional view of a dummy element for checking the dielectric breakdown voltage of a gate oxide film. 11.21.31.41-MOS type semiconductor device (chip), 12,22.32...External lead extraction terminal, 1
3.23.33... Peripheral circuit, 1525.35.45
...Measurement terminal for gate oxidation and membrane insulation voltage check,
26... Conductive polycrystalline silicon layer, 42... Semiconductor wafer, 10... Semiconductor substrate, 20... Field oxide film, 30... Gate oxide film, 40... Conductive polycrystalline silicon Layer, 50...insulating film.兇 1

Claims (1)

[Claims] In a MOS type semiconductor device having a dummy element having a MOS structure for checking the gate oxide film dielectric strength voltage in a part of the chip and a measurement terminal which is the gate electrode of the dummy element,
A MOS type semiconductor device, wherein the measurement terminal is provided in the same arrangement area as external lead extraction terminals arranged on the chip.