JPS629940B2 - - Google Patents

Info

Publication number
JPS629940B2
JPS629940B2 JP55153243A JP15324380A JPS629940B2 JP S629940 B2 JPS629940 B2 JP S629940B2 JP 55153243 A JP55153243 A JP 55153243A JP 15324380 A JP15324380 A JP 15324380A JP S629940 B2 JPS629940 B2 JP S629940B2
Authority
JP
Japan
Prior art keywords
instruction
interrupt
storage device
microprocessor
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55153243A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5776639A (en
Inventor
Toshio Yanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP55153243A priority Critical patent/JPS5776639A/ja
Publication of JPS5776639A publication Critical patent/JPS5776639A/ja
Publication of JPS629940B2 publication Critical patent/JPS629940B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP55153243A 1980-10-31 1980-10-31 Microcomputer emulator Granted JPS5776639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55153243A JPS5776639A (en) 1980-10-31 1980-10-31 Microcomputer emulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55153243A JPS5776639A (en) 1980-10-31 1980-10-31 Microcomputer emulator

Publications (2)

Publication Number Publication Date
JPS5776639A JPS5776639A (en) 1982-05-13
JPS629940B2 true JPS629940B2 (enExample) 1987-03-03

Family

ID=15558182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55153243A Granted JPS5776639A (en) 1980-10-31 1980-10-31 Microcomputer emulator

Country Status (1)

Country Link
JP (1) JPS5776639A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62183253U (enExample) * 1986-05-12 1987-11-20

Also Published As

Publication number Publication date
JPS5776639A (en) 1982-05-13

Similar Documents

Publication Publication Date Title
US8170859B1 (en) Methods, apparatuses and computer program products for simulating arbitrary unmodified code
US5619704A (en) Asynchronous interrupt inhibit method and apparatus for avoiding interrupt of an inseparable operation
US20020144235A1 (en) Debugging embedded systems
JP2655615B2 (ja) 情報処理装置
KR100238917B1 (ko) 마이크로프로세서장치 및 그 동작 관리 방법
JPH0447856B2 (enExample)
JPS629940B2 (enExample)
US7457986B2 (en) Apparatus and method for using variable end state delay to optimize JTAG transactions
JPS586971B2 (ja) 演算処理装置
JPH0646380B2 (ja) 情報処理装置
CN101154211A (zh) 嵌入式系统及其操作方法
JPS59133655A (ja) アドレス・ストツプ制御回路
JPH0573296A (ja) マイクロコンピユータ
JP2624798B2 (ja) 処理装置のデバッグ機構
KR950005523B1 (ko) 프로그램어블 로직 콘트롤러의 스텝 런 처리방법
JPS6310444B2 (enExample)
JPS62130427A (ja) メモリリ−ド／ライト方式
JPH01274253A (ja) ソフトウェアブレーク方式
JPH06103110A (ja) ブレークポイント設定方式
JPS63197247A (ja) マイクロプログラム制御装置
JPS62197834A (ja) マイクロプログラム制御装置
JPS6198455A (ja) デバイスシミユレ−ト方式
JPH01240941A (ja) 情報処理装置
JPH07271608A (ja) 割込み発生回路
JPH01309138A (ja) インサーキット・エミュレータ