JPS6298747A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the formation of a stable contact hole having no step difference and a long-lived device wherein a solid-phase epitaxial growth is never generated by burying the contact hole by a selective and epitaxial growth method. CONSTITUTION:A process; wherein an SiO2 insulating layer 2 is applied on an Si semiconductor base 1, a contact hole 3 is opened in the insulating layer 2, the contact hole 3 is buried by a selective and epitaxial growth method to grow a semiconductor layer (Si epitaxial layer) 4 and a polycrystalline semiconductor (poly Si) layer 5 and an Al (Si) conductive layer 6 are applied on the semiconductor layer 4; is included. That is, the poly Si layer 5 is inserted between the Si epitaxially grown layer 4 buried and the Al layer 6 and a solid- phase epitaxial layer is prevented from growing between the grown layer 4 and the Al layer 6. Accordingly, the poly Si layer 5 works as a solid-phase epitaxial growth obstructing layer.

Description

[Detailed Description of the Invention] [(Already required)] An epitaxial semiconductor layer is formed in a contact hole formed in a semiconductor substrate or an insulating layer deposited on a semiconductor base such as a semiconductor layer deposited on a semiconductor substrate. In the method of flattening the substrate by embedding and depositing a conductive layer thereon, in order to prevent a solid-phase epitaxial layer from growing between the epitaxial semiconductor layer and the conductive layer and increasing contact resistance, a layer is formed between the layers. A method of sandwiching a polycrystalline semiconductor layer or an impurity-introduced layer will be proposed.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device including a substrate planarization step of burying a semiconductor single crystal in a contact hole.

In a method for manufacturing a semiconductor device, a contact hole is opened in an insulating layer deposited on a semiconductor base, and a conductive layer is deposited to cover the contact hole to establish an electrical connection between the semiconductor base and the conductive layer. A process is always included.

As devices become more highly integrated and miniaturized, and the width of the contact hole becomes smaller relative to the depth and thickness of the insulating layer, it becomes difficult to cover the step with the conductive layer due to the step of the contact hole during this process. This may cause device reliability problems such as wire breakage, and the unevenness of the conductive layer deposited on the step may make it difficult to form the next film or reduce the degree of doping of the next film.

Therefore, a so-called substrate planarization process is performed in which the contact hole is filled with a conductive material and planarized, and then a conductive layer is deposited.

For example, when silicon (Si) is used as the semiconductor base, the filling material is polycrystalline silicon (poly-Si) produced by chemical vapor deposition (CVD), or single crystal S produced by selective epitaxial growth.
There are i etc. All of these are doped to make them highly conductive.

The poly-Si embedding can be easily performed by the CVD method, and a solid-phase epitaxial layer that inhibits contact is not generated at the interface with the conductive layer that is then deposited thereon. However, if the crystal grains become too large, there is a drawback that the subsequent film formation will be hindered.

The quasi-crystalline Si is buried in silicon dioxide (SiOz) in the insulating layer.
This is done using the so-called selective epitaxial growth method in which single crystal Si is selectively grown only on the exposed underlying Si without growing on the layer. In this case, high conductivity is obtained by doping the holes, and the surface of the growing layer is Although it is flat, smooth, and cleanly buried and facilitates subsequent film formation, it has the disadvantage that a solid phase epitaxial layer is formed at the interface with the conductive layer, which impedes contact.

[Conventional technology]

FIG. 3 is a cross-sectional view illustrating a conventional contact forming method in which a contact hole is filled by selective epitaxial growth.

In the figure, 1 is a semiconductor substrate, which is a Si substrate, IA is an n layer formed in the Si substrate, 2 is an insulating layer, which is a SiO□ layer, and 3 is an insulating layer.
4 is a contact hole opened in the 5in2 layer 2, 4 is a Si epitaxial growth layer, 6 is a conductive layer and is a Si-containing aluminum (A1) layer, and 8 is an in-phase epitaxial layer.

In such a structure, as described above, the p-type solid phase epitaxial layer 8 grows on the Si epitaxial growth layer 4 so as to narrow the contact hole from the periphery of the contact hole, causing an increase in contact resistance. .

[Problem that the invention seeks to solve]

In a contact formation method in which a contact hole is filled by selective epitaxial growth, a solid phase epitaxial layer grows and obstructs the contact.

[Means for resolving the problem)] The solution to the above problem is to add an insulating layer (2) on the semiconductor base (1).
), a contact hole (3) is opened in the insulating layer (2), and a semiconductor layer (4) is grown by filling the inside of the contact hole (3) by selective epitaxial growth. ) A method for manufacturing a semiconductor device comprising the steps of depositing a polycrystalline semiconductor layer (5) and a conductive layer (6) on the substrate, and depositing an insulating layer (2) on the semi-quad base (1), The insulating layer (
A contact hole (3) is opened in 2), a semiconductor layer (4) is grown by filling the inside of the contact hole (3) by selective epitaxial growth, and an impurity is introduced near the surface of the semiconductor layer (4). This is achieved by a method for manufacturing a semiconductor device including the steps of forming an introduced layer (7) and depositing a conductive layer (6) on the impurity introduced layer (7).

[Effect]

In the present invention, a solid phase epitaxial layer is grown between the S1 epitaxial growth layer and the A1 layer by inserting a poly-Si layer between the buried Si epitaxial growth layer and the first layer, or by forming a four-layer impurity layer on the surface of the Si epitaxial growth layer. This is to prevent them from doing so. Therefore, the poly-Si layer or the impurity-introduced layer acts as a blocking layer for in-phase epitaxial growth.

There is no established theory as to the reason for this, but qualitatively it can be considered as follows.

Nuclei are required for in-phase epitaxial growth, and countless such nuclei are distributed in the poly-Si or impurity-introduced layer, but in the single-crystal Si epitaxial growth layer, such nuclei are not present due to contamination, for example. The number of places where it has been received is extremely small, and it seems that it is concentrated in those places and begins to grow beyond a certain potential.

〔Example〕

FIG. 1 is a sectional view illustrating a contact forming method in which a contact hole is filled by selective epitaxial growth according to the first invention.

In the figure, 1 is a semiconductor base and is a Si substrate, IA is an n'' layer formed in the Si substrate, and 2 is an insulating layer with a thickness of 1 μm.
iO□ layer, 3 is a contact hole opened in 5iOJi2, 4 is a semiconductor layer and is a Si epitaxial growth layer, 5 is a polycrystalline semiconductor layer and is a highly doped poly-Si layer with a thickness of 2000 nm, and 6 is a conductive layer. There are 41 Si-containing layers with a thickness of 1 μm.

The growth conditions for the Si epitaxial growth layer 4 are such that silane trichloride (SiHC1+) and hydrogen (H2) are used as reaction gases, the pressure is reduced to 100 Pa, and thermal decomposition is performed at 950°C.

The poly-Si layer 50 CVD conditions are performed by using monosilane (Sil14) as a reaction gas, reducing the pressure to 100 Pa, and thermally decomposing it at 620°C.

At this time, poly5iJW5 has W (P),
Dope with boron (B), titanium (Ti), tungsten, carbon (C), etc.

In such a structure, even if accelerated conditions for solid-phase epitaxial growth (400°C, 240 hours) are applied, Si
A p' type solid phase epitaxial layer does not grow between the epitaxial growth layer 4 and the Si-containing 41 layer 6.

FIG. 2 is a cross-sectional view illustrating a contact forming method in which a contact hole is filled by selective epitaxial growth according to the second invention.

In the figure, 1 is a semiconductor base and is a Si substrate, IA is an n'' layer formed in the Si substrate, and 2 is an insulating layer with a thickness of 1 μm.
iOzlE! , 3 is a contact hole opened in the Si layer 2, 4 is a semiconductor layer and is a Si epitaxial growth layer, 7 is an impurity-introduced layer doped with Ti at a high concentration near the surface of the Si epitaxial growth layer 4, and 6 is a conductive layer with a thickness This is a Si-containing A1 layer with a thickness of 1 μm.

Even in such a structure, Si epitaxial growth N
A p-type solid-phase epitaxial layer does not grow between the Si-containing 41 layer 4 and the Si-containing 41 layer 6.

〔Effect of the invention〕

As described in detail above, in the contact forming method according to the present invention in which the contact hole is filled by selective epitaxial growth, the solid phase epitaxial layer does not grow, so the contact resistance does not increase.

Therefore, stable contact formation without steps and a long-life device without in-phase epitaxial growth can be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view illustrating a contact forming method in which a contact hole is filled by selective epitaxial growth according to the first invention, and FIG. FIG. 3 is a cross-sectional view illustrating a contact forming method in which a contact hole is filled by selective epitaxial growth according to a conventional example. In the figure, 1 is a semiconductor base which is a Si substrate, IA is an n'' layer formed in the Si substrate, 2 is a t'!! edge layer which is a SiO□ layer, 3 is a contact hole opened in the SiO□ layer 2, 4 is a semiconductor layer, which is a Si epitaxial growth layer, 5 is a polycrystalline semiconductor layer, which is a poly-Si layer, 6 is a conductive layer, which is a 41 layer containing Si, and 7 is an impurity-introduced layer.

Claims (2)

[Claims] (1) An insulating layer (2) is deposited on a semiconductor base (1), a contact hole (3) is opened in the insulating layer (2), and the inside of the contact hole (3) is filled by a selective epitaxial growth method. A method for manufacturing a semiconductor device, comprising the steps of growing a layer (4) and depositing a polycrystalline semiconductor layer (5) and a conductive layer (6) on the semiconductor layer (4). (2) An insulating layer (2) is deposited on the semiconductor base (1), a contact hole (3) is opened in the insulating layer (2), and the inside of the contact hole (3) is filled by selective epitaxial growth. growing a semiconductor layer (4) and introducing impurities near the surface of the semiconductor layer (4) to form an impurity-introduced layer (7);
A method for manufacturing a semiconductor device, comprising the step of depositing a conductive layer (6) on the impurity-introduced layer (7).