JPH065541A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH065541A JPH065541A JP16106692A JP16106692A JPH065541A JP H065541 A JPH065541 A JP H065541A JP 16106692 A JP16106692 A JP 16106692A JP 16106692 A JP16106692 A JP 16106692A JP H065541 A JPH065541 A JP H065541A
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- Prior art keywords
- silicon
- film
- opening
- selective growth
- semiconductor device
- Prior art date
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に、シリコン(Si)基板上の絶縁膜に設け
られた開口部に選択的に多結晶Si膜を成長させること
によって電極を形成する方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method for forming an electrode by selectively growing a polycrystalline Si film in an opening provided in an insulating film on a silicon (Si) substrate. It relates to a method of forming.
【0002】[0002]
【従来の技術】従来、Si基板上の絶縁膜開口部をSi
膜で選択的に埋設する技術としては、Si単結晶の選択
エピタキシャル成長が広く知られている。選択成長自体
は、Si原料ガスであるシラン系ガス(例えばSiH2
Cl2 )とエッチングガス(例えばHCl)との流量比
を制御し、成長とエッチングのバランスを調整すること
で達成される。すなわち、開口部のSi成長を維持しな
がら、絶縁膜上に形成されるSi堆積の核(極めて微小
なSi粒)をエッチングすることで選択成長が可能とな
る。2. Description of the Related Art Conventionally, the opening of an insulating film on a Si substrate is
As a technique for selectively burying with a film, selective epitaxial growth of Si single crystal is widely known. The selective growth itself is performed by using a silane-based gas (for example, SiH 2
This is achieved by controlling the flow rate ratio between Cl 2 ) and the etching gas (for example, HCl) to adjust the balance between growth and etching. That is, selective growth becomes possible by etching the nuclei of Si deposition (very small Si particles) formed on the insulating film while maintaining the Si growth in the openings.
【0003】しかしながら、近年、超高速バイポーラト
ランジスタに採用されている多結晶Siエミッタ電極を
自己整合的に形成させるには、エミッタ開口部に多結晶
Siを選択成長させる技術が重要となってきている。However, in recent years, in order to form the polycrystalline Si emitter electrode employed in the ultra-high speed bipolar transistor in a self-aligned manner, a technique of selectively growing polycrystalline Si in the emitter opening has become important. .
【0004】これは、多結晶Si中の不純物(例えば、
As)の拡散係数が単結晶中の拡散係数より大きいため
に、低温・短時間の熱処理で浅いエミッタを形成するの
に有利であること、多結晶Si/Si基板界面に好まし
くないキャリア注入を妨ぐ障壁が形成されることによる
ものであり、Aoyama等によるデバイス応用例も報
告されている(T.Aoyama et al. “S
elective Polysilicon Depo
sition(SPD) by Hot−Wall L
PCVD and Its application
to HighSpeed Bipolar Devi
ces”,Extended Abstracts o
f the 22nd Conference on
Solid State Devices and M
aterials,1990,pp665)。This is because impurities in polycrystalline Si (for example,
Since the diffusion coefficient of As is larger than that of single crystal, it is advantageous to form a shallow emitter by heat treatment at low temperature for a short time, and prevents unfavorable carrier injection at the interface of polycrystalline Si / Si substrate. This is due to the formation of a protective barrier, and a device application example by Aoyama et al. Has also been reported (T. Aoyama et al. “S.
elective Polysilicon Depo
position (SPD) by Hot-Wall L
PCVD and Its application
to HighSpeed Bipolar Devi
ces ”, Extended Abstracts o
f the 22nd Conference on
Solid State Devices and M
materials, 1990, pp665).
【0005】この報告では、750〜850℃の反応温
度領域でSiH2 Cl2 /HCl/H2 の混合ガス系を
用い多結晶Siの選択成長を実現している。この時、一
定の成長温度・圧力条件下で、HCl混合比を小さくと
ると成長速度は増加するが、臨界混合比より小さい比を
とると選択性が損なわれる。また、HCl混合比を大き
くとると成長速度が著しく低下し、成長する多結晶Si
の結晶粒が大粒径化し、結晶欠陥を多く含む単結晶に類
似した膜の結晶構造をとる。従って、HCl混合比を調
整し、高い成長速度を保ちながら極力小さな結晶粒の多
結晶Siの選択成長を行っている。In this report, selective growth of polycrystalline Si is realized in a reaction temperature range of 750 to 850 ° C. using a mixed gas system of SiH 2 Cl 2 / HCl / H 2 . At this time, under a constant growth temperature / pressure condition, if the HCl mixing ratio is made small, the growth rate increases, but if the ratio is made smaller than the critical mixing ratio, the selectivity is impaired. In addition, when the mixing ratio of HCl is increased, the growth rate is significantly reduced, and the growing polycrystalline Si
Has a large crystal grain size and has a crystal structure of a film similar to a single crystal containing many crystal defects. Therefore, the HCl mixing ratio is adjusted to selectively grow polycrystalline Si having crystal grains as small as possible while maintaining a high growth rate.
【0006】また、選択成長した膜の単結晶化を妨げる
目的で、成長用の反応ガス(例えば、SiHCl3 /H
2 混合ガス)に窒素、酸素、炭素原子を含む化合物(例
えば、アンモニアガス)を添加し、Siの単結晶化を妨
げ多結晶化する方法が提案されている(特開昭61−1
31434号公報)。これは、選択成長されたSi膜中
にSi窒化物が形成され、これがSiのエピタキシャル
成長を妨げることによる。Further, in order to prevent single crystallization of the selectively grown film, a reaction gas for growth (eg, SiHCl 3 / H) is used.
A method has been proposed in which a compound containing nitrogen, oxygen, and a carbon atom (for example, ammonia gas) is added to 2 mixed gas) to prevent single crystallization of Si and polycrystallize (JP-A-61-1).
No. 31434). This is because Si nitride is formed in the selectively grown Si film, which hinders the epitaxial growth of Si.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、従来の
多結晶Si選択成長では、選択しうるHCl混合比の範
囲が狭く、被選択成長基板の表面状態のわずかな変化
(例えば、極微量の有機系不純物の付着、自然酸化膜の
成長のばらつき等)で、選択性が損なわれたり、あるい
は成長した多結晶Siの結晶粒が巨大化するというよう
に、選択性・膜質制御の再現性が劣っているという課題
がある。However, in the conventional polycrystalline Si selective growth, the range of the selectable HCl mixing ratio is narrow, and a slight change in the surface state of the selective growth substrate (for example, an extremely small amount of organic system). Due to the adhesion of impurities, the variation in the growth of the natural oxide film, etc., the selectivity is impaired, or the grown polycrystalline Si crystal grains become large. There is a problem that
【0008】また、反応ガス中に窒素、酸素、炭素を混
合する方法では、成長した多結晶Si膜中にエピタキシ
ャル成長を阻害するためのSiの窒化物、酸化物、炭化
物が高密度に取り込まれるために、As等の不純物をド
ープしても電気抵抗が下がらないという不具合が生じ
る。Further, in the method of mixing nitrogen, oxygen and carbon into the reaction gas, Si nitride, oxide and carbide for inhibiting epitaxial growth are incorporated into the grown polycrystalline Si film at a high density. In addition, there arises a problem that the electric resistance does not decrease even if impurities such as As are doped.
【0009】本発明は従来の技術に内在する上記課題を
解決する為になされたものであり、従って本発明の目的
は、低電気抵抗で、且つ結晶粒の小さな多結晶Siで開
口部を埋設して電極を形成できる半導体装置の新規な製
造方法を提供することにある。The present invention has been made to solve the above problems inherent in the prior art. Therefore, the object of the present invention is to bury an opening with polycrystalline Si having a low electric resistance and small crystal grains. Another object of the present invention is to provide a novel method for manufacturing a semiconductor device capable of forming electrodes.
【0010】[0010]
【課題を解決するための手段】上記目的を達成するため
に、本発明による半導体装置の製造方法は、多結晶Si
を選択成長させるにあたり、水素もしくは塩化水素/水
素混合ガスで絶縁膜開口部の自然酸化膜を除去し、一酸
化炭素もしくは二酸化炭素をこの絶縁膜開口部へ供給し
て清浄なSi露出面にこれらを吸着、反応させてから、
選択成長を行うことを特徴としている。この時、一酸化
炭素もしくは二酸化炭素の吸着は、選択成長開始以前の
前処理工程とするか、あるいは選択成長途中でSi原料
ガス(シラン系ガス)供給を中断して一酸化炭素もしく
は二酸化炭素を流す中間処理工程とする。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is provided with polycrystalline Si.
In selective growth, hydrogen or hydrogen chloride / hydrogen mixed gas is used to remove the natural oxide film in the insulating film opening, and carbon monoxide or carbon dioxide is supplied to this insulating film opening to clean these exposed Si surfaces. After adsorbing and reacting
It is characterized by performing selective growth. At this time, the adsorption of carbon monoxide or carbon dioxide should be performed in a pretreatment step before the start of selective growth, or the supply of Si source gas (silane-based gas) should be interrupted during the selective growth to remove carbon monoxide or carbon dioxide. This is an intermediate treatment step of flowing.
【0011】[0011]
【作用】Si露出面に吸着した一酸化炭素もしくは二酸
化炭素は、下地基板(Si)と選択的に反応し、多結晶
Si炭化物(SiC)とSi酸化物の混合物が形成さ
れ、次工程で開口部に供給されるシラン系ガスによって
Siが成長しようとするときに、この混合物が下地基板
(シリコン単結晶)の結晶格子の連続性が選択成長する
シリコン膜へ伝達されるのを阻害することによって成長
するSi膜は多結晶化する。また、成長時に受ける熱処
理によりSiC、Si酸化物の混合物は極めて薄い層を
形成し、基板及び選択成長膜界面から過剰のSiが供給
されるために、基板と選択成長膜は殆んどシリコンで結
合した状態となり、電気抵抗を上昇させるような強固な
障壁を形成することは無い。The carbon monoxide or carbon dioxide adsorbed on the exposed Si surface selectively reacts with the underlying substrate (Si) to form a mixture of polycrystalline Si carbide (SiC) and Si oxide, which is opened in the next step. When Si is grown by the silane-based gas supplied to the substrate, this mixture prevents the continuity of the crystal lattice of the underlying substrate (silicon single crystal) from being transmitted to the selectively grown silicon film. The growing Si film is polycrystallized. In addition, the mixture of SiC and Si oxide forms an extremely thin layer due to the heat treatment performed during the growth, and since excess Si is supplied from the interface between the substrate and the selective growth film, the substrate and the selective growth film are almost composed of silicon. It will be in a bonded state and will not form a strong barrier that raises the electrical resistance.
【0012】[0012]
【実施例】次に、本発明をその好ましい各実施例につい
て図面を参照して具体的に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be specifically described with reference to the drawings for each of its preferred embodiments.
【0013】図1(a)〜(d)は本発明による第1の
実施例を示す工程図である。1A to 1D are process diagrams showing a first embodiment according to the present invention.
【0014】図1(a)〜(d)を参照するに、n型の
Si基板1上に熱酸化もしくは化学気相成長法によりS
i酸化膜2を形成し、さらに通常の光リソグラフィ及び
エッチング技術により開口部3を設ける。続いて、この
開口部3にn型拡散層4を形成して減圧気相成長装置に
導入する。この時、n型拡散層4上には1nm程度の自
然酸化膜5が形成されている(図1(a)参照)。Referring to FIGS. 1 (a) to 1 (d), S is formed on an n-type Si substrate 1 by thermal oxidation or chemical vapor deposition.
An i-oxide film 2 is formed, and an opening 3 is further provided by a usual photolithography and etching technique. Then, the n-type diffusion layer 4 is formed in the opening 3 and introduced into the low pressure vapor phase growth apparatus. At this time, a natural oxide film 5 of about 1 nm is formed on the n-type diffusion layer 4 (see FIG. 1A).
【0015】続いて、減圧気相成長装置内に水素を導入
し、850℃、0.5torrで処理し、自然酸化膜5
を除去し、二酸化炭素/不活性ガス(例えばアルゴン、
ヘリウム、窒素)の混合ガスを導入し850℃、1to
rrでn型拡散層上に二酸化炭素を吸着・反応させる。
この時、混合ガス中の二酸化炭素濃度や吸着時の温度・
圧力は任意に設定できるが、混合ガス導入と同時に開口
底部にSiC、Si酸化物の混合物の層6が数nm、望
ましくは2nm以下の厚さで形成されるように調整する
必要がある(図1(b)参照)。Subsequently, hydrogen was introduced into the reduced pressure vapor phase growth apparatus and treated at 850 ° C. and 0.5 torr to form the natural oxide film 5.
Carbon dioxide / inert gas (eg argon,
Introduce a mixed gas of helium and nitrogen) at 850 ° C., 1 to
Carbon dioxide is adsorbed and reacted on the n-type diffusion layer by rr.
At this time, the concentration of carbon dioxide in the mixed gas and the temperature during adsorption
The pressure can be set arbitrarily, but it is necessary to adjust so that the layer 6 of the mixture of SiC and Si oxide is formed at a thickness of several nm, preferably 2 nm or less at the bottom of the opening at the same time when the mixed gas is introduced (Fig. 1 (b)).
【0016】この後、ジクロルシラン/塩化水素/水素
(SiH2 Cl2 /HCl/H2 )混合ガスを流すこと
で多結晶Si7を選択的に開口部のみに成長させる(図
1(c)参照)。この時の成長条件は下記の如くであ
る。Thereafter, a mixed gas of dichlorosilane / hydrogen chloride / hydrogen (SiH 2 Cl 2 / HCl / H 2 ) is flown to selectively grow the polycrystalline Si 7 only in the openings (see FIG. 1 (c)). . The growth conditions at this time are as follows.
【0017】 ガス流量 SiH2 Cl2 400 sccm HCl 350 sccm H2 10 SLM 成長温度/圧力 800℃/100 to
rr この後にひ素を70keV,5×1015/cm2 でイオ
ン注入し、1000℃で5分間の熱処理を施してアルミ
ニウム等の金属で配線8を形成する(図1(d)参
照)。Gas flow rate SiH 2 Cl 2 400 sccm HCl 350 sccm H 2 10 SLM Growth temperature / pressure 800 ° C./100 to
rr After that, arsenic is ion-implanted at 70 keV and 5 × 10 15 / cm 2 , and heat treatment is performed at 1000 ° C. for 5 minutes to form the wiring 8 with a metal such as aluminum (see FIG. 1D).
【0018】表1は、第1の実施例におけるコンタクト
抵抗を示すものであり、Si選択成長の原料ガスにアン
モニアを混合する従来技術で開口部を埋設したものを参
照試料としている。Table 1 shows the contact resistance in the first embodiment, and the reference sample is a sample in which the opening is buried by the conventional technique of mixing ammonia with the source gas for Si selective growth.
【0019】[0019]
【表1】 ─────────────────────────────── 混合物の厚さ(nm) 抵抗(Ω) ─────────────────────────────── 本実施例 1 20〜45 2 20〜50 4 45〜80 6 80〜150 10 100〜200 従来技術 − 400〜2000 ─────────────────────────────── この時のコンタクトサイズは、0.8μm×1.5μm
である。[Table 1] ─────────────────────────────── Mixture thickness (nm) Resistance (Ω) ──── ─────────────────────────── Example 1 1 20 to 45 2 20 to 50 4 45 to 80 6 80 to 150 10 100 to 200 Prior art −400 to 2000 ─────────────────────────────── The contact size at this time is 0.8 μm × 1. 5 μm
Is.
【0020】本発明では、単位コンタクト当たり20〜
200Ωの抵抗値が得られたのに対し、従来技術による
ものでは400〜2000Ωと高い抵抗値しか得られな
かった。また、SiCとSi酸化物の混合物層の厚さに
ついても2nm以下であれば、単位コンタクト当たりの
抵抗値が50Ω以下に安定に抑えられることが分かる。In the present invention, 20 to 20 per unit contact
While a resistance value of 200Ω was obtained, a resistance value as high as 400 to 2000Ω was obtained by the conventional technique. Also, it can be seen that if the thickness of the mixture layer of SiC and Si oxide is 2 nm or less, the resistance value per unit contact can be stably suppressed to 50Ω or less.
【0021】また、SiC、Si酸化物の混合物の層を
形成しない場合と本実施例の場合について、選択成長し
たSiを透過型電子顕微鏡で結晶粒を観察した結果、本
実施例では幅0.2〜0.5μm程度の柱状結晶粒が観
察されたが、SiC/Si酸化物の混合物の層を形成し
なかった場合では、ほとんど結晶粒界は観察されず、本
実施例は選択成長膜の微小結晶粒の多結晶形成に効果の
あることが確認された。Further, as a result of observing the crystal grains of the selectively grown Si with a transmission electron microscope in the case of not forming a layer of a mixture of SiC and Si oxide and in the case of this embodiment, in the present embodiment, a width of 0. Columnar crystal grains of about 2 to 0.5 μm were observed, but almost no crystal grain boundaries were observed when the layer of the mixture of SiC / Si oxide was not formed. It was confirmed that it was effective in forming a polycrystal of fine crystal grains.
【0022】なお、本実施例ではSiC、Si酸化物の
混合物層形成に二酸化炭素を用いたが、一酸化炭素を用
いても同等の結果がえられる。またこれらのガスは純ガ
スを利用することも可能である。Although carbon dioxide was used to form the mixture layer of SiC and Si oxide in this example, the same result can be obtained by using carbon monoxide. It is also possible to use pure gas as these gases.
【0023】図2(a)〜(d)は、本発明による第2
の実施例を示す工程図である。2 (a)-(d) show a second embodiment of the present invention.
FIG. 6 is a process drawing showing an example of FIG.
【0024】図2(a)〜(d)を参照するに、p型の
Si基板11上に熱酸化もしくは化学気相成長法により
Si酸化膜12を形成し、さらに通常の光リソグラフィ
及びエッチング技術により開口部13を設ける。続い
て、この開口部にn型拡散層14を形成して減圧気相成
長装置に導入する。この時、n型拡散層上には1nm程
度の自然酸化膜15が形成されている(図2(a)参
照)。Referring to FIGS. 2A to 2D, a Si oxide film 12 is formed on a p-type Si substrate 11 by thermal oxidation or chemical vapor deposition, and then ordinary photolithography and etching techniques are used. The opening 13 is provided by. Subsequently, the n-type diffusion layer 14 is formed in this opening and introduced into the low pressure vapor phase growth apparatus. At this time, the natural oxide film 15 of about 1 nm is formed on the n-type diffusion layer (see FIG. 2A).
【0025】続いて、減圧気相成長装置内に塩化水素
(1%)/水素混合ガスを導入し、850℃、0.5t
orrで処理し、n型拡散層上の自然酸化膜を除去す
る。この時塩化水素/水素混合ガスの代わりにふっ化水
素あるいはふっ化水素/水素蒸気混合ガスを使用するこ
とも可能であるが、これらのガスを用いる場合には処理
温度を室温付近の低温とする。Subsequently, a hydrogen chloride (1%) / hydrogen mixed gas was introduced into the reduced pressure vapor phase growth apparatus, and 850 ° C., 0.5 t.
Then, the natural oxide film on the n-type diffusion layer is removed. At this time, it is possible to use hydrogen fluoride or hydrogen fluoride / hydrogen vapor mixed gas in place of the hydrogen chloride / hydrogen mixed gas, but when using these gases, the treatment temperature should be a low temperature near room temperature. .
【0026】次に、前記第1の実施例と同様の条件で開
口部に5nmの厚さに第1のSi選択成長膜16を形成
する(図2(b)参照)。Next, a first Si selective growth film 16 having a thickness of 5 nm is formed in the opening under the same conditions as in the first embodiment (see FIG. 2B).
【0027】次に、一酸化炭素/不活性ガス(例えばア
ルゴン、ヘリウム、窒素)の混合ガスを導入し850
℃、1torrで開口底部のSi露出部に一酸化炭素を
吸着・反応させる。この際にも、混合ガス中の一酸化炭
素濃度や吸着時の温度・圧力は任意に設定できるが、低
抵抗化を実現するため混合ガス導入と同時に開口底部に
SiC、Si酸化物の混合物17は、望ましくは2nm
以下の厚さで形成されるように調整する必要がある(図
2(c)参照)。Next, a carbon monoxide / inert gas (eg, argon, helium, nitrogen) mixed gas is introduced 850.
Carbon monoxide is adsorbed and reacted on the exposed Si portion at the bottom of the opening at 1 ° C. and 1 ° C. Also in this case, the concentration of carbon monoxide in the mixed gas and the temperature / pressure at the time of adsorption can be set arbitrarily, but in order to realize low resistance, at the same time when the mixed gas is introduced, a mixture of SiC and Si oxide 17 is formed at the bottom of the opening. Is preferably 2 nm
It is necessary to adjust it so that it is formed with the following thickness (see FIG. 2C).
【0028】続いて、先のSi選択成長膜形成と同条件
で第2のSi選択成長膜18を形成する。この時第2の
Si選択成長膜18は、前記第1の実施例と同様に多結
晶Siとなる。この後ひ素を70keV,5×1015/
cm2 でイオン注入し、1000℃で5分間の熱処理を
施してアルミニウム等の金属で配線19を形成する(図
2(d)参照)。Then, a second Si selective growth film 18 is formed under the same conditions as the above-mentioned Si selective growth film formation. At this time, the second Si selective growth film 18 becomes polycrystalline Si as in the first embodiment. After this, arsenic was changed to 70 keV, 5 × 10 15 /
Ion implantation is performed at a cm 2 and heat treatment is performed at 1000 ° C. for 5 minutes to form the wiring 19 with a metal such as aluminum (see FIG. 2D).
【0029】この第2の実施例は、Siの選択成長を2
段階で行う点で前記第1の実施例と異なっている。第1
のSi選択成長によってSiC、Si酸化物の混合物が
形成される位置が、本来、Si基板表面であった位置よ
り上部に持ち上げられており、SiC、Si酸化物の混
合物によって生ずる歪が直接Si基板に及ばなくなる。
この結果、pn接合リークの原因となる結晶欠陥の発生
が抑制される。In the second embodiment, the selective growth of Si is performed in two steps.
It differs from the first embodiment in that it is performed in stages. First
The position where the mixture of SiC and Si oxide is formed by the selective Si growth of Si is raised above the position where it was originally the surface of the Si substrate, and the strain caused by the mixture of SiC and Si oxide is directly generated on the Si substrate. Will not reach.
As a result, generation of crystal defects that cause pn junction leakage is suppressed.
【0030】表2は第1の実施例を参照試料とし、面積
1×10-2cm2 、周囲長40cmの櫛型拡散層におけ
るpn接合リークを測定した結果である。本実施例のリ
ーク電流は、1〜6×10-9A/cm2 であったのに対
し、参照試料では5〜75×10-9A/cm2 であり、
第2の実施例により、pn接合リークを低減できること
が確かめられた。Table 2 shows the results of measuring the pn junction leak in the comb-shaped diffusion layer having an area of 1 × 10 -2 cm 2 and a perimeter of 40 cm, using the reference sample of the first embodiment. The leak current of this example was 1 to 6 × 10 −9 A / cm 2 , whereas the leak current of the reference sample was 5 to 75 × 10 −9 A / cm 2 ,
It was confirmed that the pn junction leakage can be reduced by the second example.
【0031】[0031]
【表2】 ─────────────────────────── リーク電流 ─────────────────────────── 本実施例 1〜6×10-9A/cm2 参照試料 5〜75×10-9A/cm2 (第1実施例) ─────────────────────────── なお、本実施例ではSiC、Si酸化物の混合物層形成
に一酸化炭素を用いたが、二酸化炭素を用いても同時の
結果がえられる。また、第1の実施例と同様に、純ガス
の使用も可能である。[Table 2] ─────────────────────────── Leakage current ───────────────── ────────── Example 1-6 × 10 -9 A / cm 2 Reference sample 5-75 × 10 -9 A / cm 2 (first example) ─────── ──────────────────── In addition, although carbon monoxide was used for forming the mixture layer of SiC and Si oxide in this example, carbon dioxide may be used. Simultaneous results can be obtained. Further, as in the first embodiment, it is possible to use pure gas.
【0032】[0032]
【発明の効果】以上説明したように、本発明によれば、
選択成長に先立ち、選択成長させようとするSi露出面
に成長した自然酸化膜を除去し、SiC/Si酸化物の
混合物層を形成した後にSiを選択成長することで、成
長した膜を微小結晶粒の多結晶としコンタクト抵抗を低
抵抗化することができる。As described above, according to the present invention,
Prior to the selective growth, the natural oxide film grown on the exposed Si surface to be selectively grown is removed, and a mixed layer of SiC / Si oxide is formed, and then Si is selectively grown to form a microcrystal of the grown film. The contact resistance can be lowered by using polycrystal grains.
【0033】また、本発明によれば、Si選択成長を2
段階に分け、第1のSi選択成長の後にSiC/Si酸
化物の混合物層を形成することで、Si選択成長膜下に
あるpn接合のリーク電流を低減することが可能とな
る。Further, according to the present invention, Si selective growth is performed to 2
By dividing into stages and forming a mixture layer of SiC / Si oxide after the first Si selective growth, it becomes possible to reduce the leak current of the pn junction under the Si selective growth film.
【図1】(a)〜(d)は本発明による第1の実施例の
工程を示す概略図である。1A to 1D are schematic views showing steps of a first embodiment according to the present invention.
【図2】(a)〜(d)は本発明による第2の実施例の
工程を示す概略図である。2 (a) to (d) are schematic views showing steps of a second embodiment according to the present invention.
1…n型Si基板 2…Si酸化膜 3…開口部 4…n型拡散層 5…自然酸化膜 6…SiC/Si酸化物の混合物層 7…多結晶Si 8…Al配線 11…p型Si基板 12…Si酸化膜 13…開口部 14…n型拡散層 15…自然酸化膜 16…第1のSi選択成長膜 17…SiC/Si酸化物の混合物層 18…第2のSi選択成長膜 19…Al配線 DESCRIPTION OF SYMBOLS 1 ... n-type Si substrate 2 ... Si oxide film 3 ... opening 4 ... n type diffusion layer 5 ... natural oxide film 6 ... SiC / Si oxide mixture layer 7 ... polycrystalline Si 8 ... Al wiring 11 ... p type Si Substrate 12 ... Si oxide film 13 ... Opening portion 14 ... N-type diffusion layer 15 ... Natural oxide film 16 ... First Si selective growth film 17 ... SiC / Si oxide mixture layer 18 ... Second Si selective growth film 19 ... Al wiring
Claims (4)
リコン基板の露出した開口部のみに選択的に多結晶シリ
コンを成長させる半導体装置の製造方法において、 開口部底面に形成されている自然酸化膜を除去する工程
と、該開口部底面にシリコン炭化物/シリコン酸化物の
混合物層を形成する工程とを経た後に多結晶シリコンを
選択成長させることを特徴とする半導体装置の製造方
法。1. A method of manufacturing a semiconductor device in which polycrystalline silicon is selectively grown only in an exposed opening of a silicon substrate provided in an insulating film on a silicon substrate, wherein natural oxidation formed on the bottom surface of the opening. A method of manufacturing a semiconductor device, which comprises selectively growing polycrystalline silicon after a step of removing a film and a step of forming a mixture layer of silicon carbide / silicon oxide on a bottom surface of the opening.
リコン基板の露出した開口部のみに選択的にシリコンを
成長させる半導体装置の製造方法において、 開口部底面に形成されている自然酸化膜を除去する工程
と、該開口部底面にシリコン選択成長膜を形成する工程
と、該シリコン選択成長膜上にシリコン炭化物/シリコ
ン酸化物の混合物層を形成する工程とを経た後に多結晶
シリコンを選択成長させることを特徴とする半導体装置
の製造方法。2. A method of manufacturing a semiconductor device in which silicon is selectively grown only in an exposed opening of a silicon substrate provided in an insulating film on a silicon substrate, wherein a natural oxide film formed on a bottom surface of the opening is formed. Selective growth of polycrystalline silicon is performed after a step of removing, a step of forming a silicon selective growth film on the bottom surface of the opening, and a step of forming a silicon carbide / silicon oxide mixture layer on the silicon selective growth film. A method for manufacturing a semiconductor device, comprising:
は塩化水素/水素混合ガス雰囲気中で行われることを更
に特徴とする請求項1または2のいずれか一項に記載の
半導体装置の製造方法。3. The method for manufacturing a semiconductor device according to claim 1, wherein the step of removing the natural oxide film is performed in an atmosphere of hydrogen or hydrogen chloride / hydrogen mixed gas. .
混合物層を形成する工程が、一酸化炭素もしくは二酸化
炭素、あるいはこれらの混合ガス、あるいはこれら単体
ガスもしくは混合ガスを不活性ガスで希釈したガス雰囲
気中で行われることを更に特徴とする請求項1または2
のいずれか一項に記載の半導体装置の製造方法。4. The step of forming the mixture layer of silicon carbide / silicon oxide comprises carbon monoxide, carbon dioxide, a mixed gas thereof, or a gas atmosphere obtained by diluting these single gases or mixed gas with an inert gas. 3. The method according to claim 1, further characterized in that
The method for manufacturing a semiconductor device according to any one of 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16106692A JPH065541A (en) | 1992-06-19 | 1992-06-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16106692A JPH065541A (en) | 1992-06-19 | 1992-06-19 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH065541A true JPH065541A (en) | 1994-01-14 |
Family
ID=15727972
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16106692A Pending JPH065541A (en) | 1992-06-19 | 1992-06-19 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH065541A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010123866A (en) * | 2008-11-21 | 2010-06-03 | Sharp Corp | Semiconductor device and method of manufacturing the same |
-
1992
- 1992-06-19 JP JP16106692A patent/JPH065541A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010123866A (en) * | 2008-11-21 | 2010-06-03 | Sharp Corp | Semiconductor device and method of manufacturing the same |
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