JPS6298354U - - Google Patents
Info
- Publication number
- JPS6298354U JPS6298354U JP19127085U JP19127085U JPS6298354U JP S6298354 U JPS6298354 U JP S6298354U JP 19127085 U JP19127085 U JP 19127085U JP 19127085 U JP19127085 U JP 19127085U JP S6298354 U JPS6298354 U JP S6298354U
- Authority
- JP
- Japan
- Prior art keywords
- parallel
- terminal
- data
- transmission device
- converter circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は本考案の別の実施例を示すブロツク図、
第３図は第２図の実施例の動作を示すタイミング
チヤートである。
１……パラレル・シリアル変換器、２……クロ
ツク発生器、１１〜１８……８ビツトの入力端子
、１９……出力端子、２１〜２５……パラレルデ
ータ入力端子、３１〜３５……パラレールデータ
入力端子の信号、３６……サンプリングクロツク
、３７……シリアル信号、４１〜４５……パラレ
ル信号。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing another embodiment of the present invention;
FIG. 3 is a timing chart showing the operation of the embodiment shown in FIG. 1...Parallel/serial converter, 2...Clock generator, 11-18...8-bit input terminal, 19...Output terminal, 21-25...Parallel data input terminal, 31-35...Parallel Data input terminal signal, 36...sampling clock, 37...serial signal, 41 to 45...parallel signal.
Claims (1)
ｍビツトのパラレル・シリアル変換回路と、ｎビ
ツトのパラレルデータ入力端子とから構成される
データ伝送装置において、前記パラレルデータ入
力端子のうち、最も高速のデータが入力される端
子が前記パラレル・シリアル変換回路の（ｍ−ｎ
＋１）本の入力端子に並列に接続されていること
を特徴とするデータ伝送装置。 m and n are positive integers, and in a data transmission device consisting of an m-bit parallel-to-serial converter circuit and an n-bit parallel data input terminal in the relationship m>n>1, the parallel data input terminal Among them, the terminal to which the fastest data is input is the (m-n) terminal of the parallel-serial converter circuit.
+1) A data transmission device characterized by being connected in parallel to two input terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19127085U JPS6298354U (en) | 1985-12-11 | 1985-12-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19127085U JPS6298354U (en) | 1985-12-11 | 1985-12-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6298354U true JPS6298354U (en) | 1987-06-23 |
Family
ID=31145255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19127085U Pending JPS6298354U (en) | 1985-12-11 | 1985-12-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6298354U (en) |
-
1985
- 1985-12-11 JP JP19127085U patent/JPS6298354U/ja active Pending
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