JPS6297349A - Wiring and forming method thereof - Google Patents

Abstract

PURPOSE:To obviate the increase in wiring thicknesses at the connecting parts of the wirings and to improve the manufacturing yield rate, by electrically connecting the wirings made of different materials by way of the wirings, which are formed on the different wiring layers using materials that does not react with the wiring of two or more different kinds of materials on the same wiring layer at a specified using temperature. CONSTITUTION:MOSFET ohmic electrodes 31a-31d comprise laminated metal of AuGe alloy having a thickness of about 0.15mum and Ni having a thickness of about 0.05mum. Gate electrode 41a-41d comprises W5Si3 having a thickness of about 0.3mum. Gate electrode metal is used for wiring from the gate electrode 41a to 41d since the wiring resistance on a circuit poses no problem. Wirings to the gate electrodes 41b and 41c are connected to first wiring layers 81a and 18b comprising W having a thickness of about 0.4mum. The connections are performed by way of second wiring layers 91c and 91e comprising a laminated metal film of Ti having a thickness of about 0.1mum, Pt having a thickness of about 0.1mum and Au having a thickness of about 0.4mum. The Ti-Pt-Au laminated metal film does not react with W5Si3 and W at the using temperature of a GaAs FET (125 deg.C). Therefore the reliability of the wirings is made excellent.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to wiring of a semiconductor device and a method of forming the same,
In particular, the present invention relates to wiring of a semiconductor device in which wiring of two or more different materials are mixedly mounted on the same layer, and a method of forming the same.

(Prior Art) Multilayer wiring technology is often used for wiring of semiconductor devices, but when wirings made of different materials are mixedly mounted on the same wiring layer, for example, a planar structure shown in FIG. 3 is used.

The figure shows a part of the planar pattern of an integrated circuit using a gallium oxide (GaAs) Schottky barrier gate field effect transistor (MESFET), 33a to 33c are AuGe alloys with a thickness of 0.15 pm, N of
Ohmic electrodes made of laminated metal films of i, 43a and 43
b is a gate electrode made of W5Si3 and having a thickness of 0.3 pm. These ohmic electrode metals and gate electrode metals have high sheet resistance values of about 3.5Ω and 6.7Ω, respectively, so they are not used as the first layer wiring. First layer interconnections 83a and 83b are formed using a laminated film made of Au with a thickness of 0.4 pm, and are electrically connected to the ohmic electrode metal and the gate electrode metal.

In addition, after forming the gate electrode and the ohmic electrode, such wiring is formed using a laminated film made of, for example, Ti with a thickness of 0.1 pm and Au with a thickness of 0.4 pm by a normal etching method or lift-off method. A one-layer wiring is formed, then a 5i02 film with a thickness of 0.5 μm is deposited by CVD, a through hole is opened by dry etching using CF4 gas, and a Ti film with a thickness of 0.1 pm and a 0.5 μm thick film are deposited. .1p
This can be obtained by forming a second layer wiring using a laminated film made of Pt with a thickness of m and Au with a thickness of 0.4 pm.

(Problems to be Solved by the Invention) In the conventional wiring described above, the metal film thickness is thicker in the overlapping part of the gate electrode and the first layer wiring, and in the overlapping part of the ohmic electrode and the first layer wiring, compared to other parts. Therefore, a big problem arises in the process of drying after depositing the interlayer insulating film. That is, in the photoresist coating process, the thickness of the coating film in the overlapped area is thinner than the other parts (which makes pinholes more likely to occur), and it is also wider (according to the contact exposure method used, the thickness of the coating film in the overlapped part is thinner than the other parts). This protrusion has the disadvantage that the photoresist in this area may adhere to the photomask.

Furthermore, in the conventional wiring formation method described above, when the first layer wiring is formed by the etching method, the thickness of the wiring at the overlapped portion is thicker than the other layers, so the photoresist film for forming the first layer wiring is This causes problems such as the layer becomes particularly thin in the overlapped portion and photoresist patterning becomes difficult in the stepped portion, and therefore it is extremely difficult to miniaturize the first layer wiring pattern in the overlapped portion. On the other hand, when forming one-layer wiring using the lift-off method, it is necessary to install a spacer material to facilitate lift-off, but it is possible to install the spacer material without affecting the characteristics of the MESFET formed on the base. Removal is not easy and poses a major manufacturing constraint.

(Means for Solving the Problems) The wiring according to the first invention of the present application has two or more types of wirings made of different materials mixedly mounted on the same wiring layer, and the wirings made of different materials do not meet the specified operating temperature. Wirings made of different materials are electrically connected to each other through wirings formed on different wiring layers of wiring layers formed using materials that do not cause reactions, and the wiring is the second invention of the present application. The formation method includes a step of forming a first wiring, a step of covering an area to be protected in a subsequent process with a cover material, a step of applying a second wiring material, and a step of forming a second wiring by etching. The process includes depositing an interlayer insulating film and opening through-holes in predetermined portions, and depositing and processing materials that do not react at a predetermined usage temperature as the first and second wiring materials. When connecting the first and second electrically, these wirings are not directly connected on the same wiring layer, but are connected via wiring formed on different wiring layers, thereby achieving direct connection. It is possible to eliminate the increase in the wiring thickness at the connection portion between the wirings, which occurs in some cases, and to solve manufacturing problems caused by the increase in the wiring thickness. In addition, since the wiring is processed after forming the etching protection film, the MESFET that has already been formed
The characteristics of the wire do not deteriorate during wiring processing.

(Example 1) Next, the wiring of the present invention will be explained with reference to the drawings, taking a GaAs MESFET as an example. FIG. 1 shows the first embodiment of the present invention.
FIG. In the figure, 31a to 31d are AuGe alloys with a thickness of 0.15 pm;
MESFE made of Ni laminated metal with a thickness of 0.05 pm
The ohmic electrodes 41a to 41d of T are 0.3 pm thick.
The gate electrode 41a is made of W5Si3.
However, the wiring leading to 41d is made of gate electrode metal since wiring resistance is not a problem in the circuit. Gate electrode 41b
The wirings to j3 and 41c are respectively connected to first layer wirings 81a and 81b made of W with a thickness of 0.4 pm, but these connections are made using a 0.1 pm thick wire formed on an interlayer insulating film.
The second layer wirings 91c and 91 are made of a laminated metal film of pm Ti, 0.1 μm thick PT, and 0.4 μm thick Au.
This is done via e. Furthermore, Tx, pt, A
u The laminated metal film has a GaAs MESFET operating temperature (12
5° C.), there is no reaction with W5Si3 and W, so the reliability of this wiring is good. According to the wiring according to the present invention, the wirings made of different materials on the first layer overlap each other (Example 2) Next, the method for forming the wiring according to the present invention will be explained with reference to the drawings. FIG. 2 is a process sectional view for explaining an embodiment of the second invention of the present invention. In the figure, 12 is a semi-insulating GaAs substrate 13, which is the total area of the GaAs MESFET;
2a and 32b are AuGe alloys with a thickness of 0.15 pm,
The ohmic electrode of MESFET, 42a, is made of laminated metal with a thickness of 0.05 pm and has a thickness of 0.3 pm. (7) W5Si
The gate electrode 52a made of 3 is formed at the same time as the gate electrode with the first layer wiring made of W5Si3 (Fig. 2(a)
)).

Next, as shown in FIG. 2(b), 5i02 films 62a and 62b with a thickness of 0.2 pm are formed by MES using an atmospheric pressure CVD method to protect them from etching during the processing of other first layer wiring in the subsequent process.
It is formed on the FET and the first layer wiring 52a.

Next, as shown in FIG. 2(e), a W film 12 having a thickness of 0.4 pm is deposited as another first layer wiring metal by sputter deposition.

Subsequently, as shown in FIG. 2(d), the first layer wiring metal 72 is processed by reactive ion etching using photoresist as a mask and using SF6 gas to form a wiring 82a, and the etching protection films 62a and 62b are etched. Remove using buffered hydrofluoric acid.

Next, as shown in FIG. 2(e), as an interlayer insulating film, a normal pressure C
A 0.3 pm thick 5i02 film 112 is deposited by the VD method, and through holes are opened at predetermined positions using CF4 gas.

Then, as shown in Figure 2 (0), the GaAs MESFET
At the operating temperature (125°C), AuGe alloy, laminated metal made of Ni, W5Si3. As a material that does not react with W, Ti with a thickness of 0.1 pm, PT with a thickness of 0.1 pm, and Pt with a thickness of 0.4 pm were sequentially deposited by sputter deposition and ion milling using photoresist as a mask. Then, second layer wirings 92a to 92c are formed, and the photoresist is removed. First layer wiring 5 made of W5Si3
The first layer wiring 82a made of 2a and W is the second layer wiring 92c.
An electrical connection is made.

According to the present invention, since the first layer wirings made of different materials do not overlap, the conventional difficulty in patterning photoresist at the wiring layer area is eliminated.
The first layer wiring pattern could also be made finer without any problem. Furthermore, since a protective film is provided using a 5i02 film grown by atmospheric pressure CVD with a thickness of 0.2 pm, there is no etching of the MESFET electrode and active layer during etching for forming the first layer wiring 82a, and there is no dry etching damage. Therefore, no deterioration of the MESFET characteristics was observed at all.

(Effects of the Invention) As explained above in detail, according to the wiring of the present invention, wirings made of different materials on the same wiring layer do not overlap, so that the wiring thickness at the portion where the wiring layer overlaps is reduced compared to the conventional wiring layer. The problem of pinholes in the photoresist film in post-processes caused by an increase in the number of photoresists has been significantly improved.

Furthermore, the problem of adhesion of the photoresist film to the photomask in the subsequent contact exposure step has been solved, and it has become possible to use the contact exposure method, which is inexpensive and has excellent productivity. In fact, ME caused by the processing process of the first layer wiring to install a protective film.
There is no characteristic deterioration of the SFET, and since the first layer wiring material and the second layer wiring material do not react at the operating temperature of the MESFET, highly reliable wiring can be realized, and the effects of the present invention are significant.

[Brief explanation of drawings]

1 and 2 are plan views and process sectional views for explaining in detail the first and second inventions of the present invention, respectively, and FIG. 3 is a plan view for explaining a conventional example. 12...Semi-insulating GaAs substrate, 31,32.33...Ohmic electrode, 41.42,4
3,... Gate electrode, 62... Etching protective film, 81.82.83... First layer wiring, 91,92.
93...Second layer wiring, 101.103...Through hole, 112...Interlayer insulating film. Director of the Agency of Industrial Science and Technology Todoroki Tatsudai / Figures /! 71 Muzurubo Zushiman 2 Figure Ra II l 92c Rough j distribution 7 Atsushi, ib Shu Z layer distribution east

Claims (1)

[Claims] 1. Two or more types of wiring made of different materials are mixed on the same wiring layer, and the wiring is formed using a material that does not react with the wiring made of these different materials at a predetermined operating temperature. A wiring characterized in that wirings made of different materials are electrically connected to each other through wirings formed on different wiring layers. 2. A step of forming a first wiring, a step of covering an area to be protected in a subsequent process with a cover material, a step of applying a second wiring material, and a step of forming a second wiring by etching. , the process of depositing an interlayer insulating film and opening through holes in predetermined portions, and depositing materials that do not react at a predetermined operating temperature as the first and second wiring materials, and processing them. A method for forming a wiring, comprising the step of forming a wiring that electrically connects a first wiring and a second wiring.