JPH01192141A - Wiring of compound semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a wiring due to the reactions of an ohmic electrode and a wiring material layer by providing the ohmic electrode with a short lead-out electrode. CONSTITUTION:A GaAs ohmic contact metal layer, which is adhered using a vacuum deposition method and has the composition of a gold-germanium alloy, for example, is formed in such a way that the layer is left on source and drain regions. Regions 6a and 6b show source and drain electrodes of a MESFET formed in such a way, but at this time, the 6a and 6b are formed in such a way that they can be respectively made an electrical contact with 4a and 4b. After this, an insulating film 11 is covered on the whole surface and contact holes 7, 8a and 8b to tungsten nitride film patterns 3, 4a and 4b are formed on this insulating film. Moreover, a patterning of Al alloy wirings 9, 10a and 10b is performed to form a self-alignment type GaAs MESFET. As an ohmic electrode 6 is connected with an Al film 10, which is a first layer wiring, through a lead-out electrode 4, the reactions of both are completely prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) This invention relates to a highly reliable wiring method for compound semiconductor devices.

(Prior art) As a conventional wiring method for compound semiconductors, it is essential to form good ohmic electrodes, such as using AuGe/Au as the main constituent material. Avoid wiring, T i / P
Au-based wiring materials such as t/Au have been used.

In addition, it is easy to infer that various barrier metals are laminated between ohmic electrodes and wiring materials for the purpose of preventing purple plaque, but the reactivity of Au-Al, which causes purple plaque, is extremely high, and Since the deterioration of the ohmic electrode due to the invasion of Aj is extremely rapid,
There is no known example of establishing a wiring technology that can withstand high-temperature accelerated life tests using this method.

(Issue to be solved by the invention@) The object of the present invention is to provide a compound semiconductor integrated circuit having a heat-resistant metal as a gate and an Au-based ohmic electrode, in which a 5iVL is used instead of an Au-based wiring which has poor microfabriability.
The Aj-based wiring technology, which has a proven track record in SI, can be applied to almost the same extent without increasing the number of processes (,
The present invention aims to provide a means for completely preventing the Au-Aj reaction in the ohmic electrode section.

[Structure of the invention]

(Means for Solving Problem 11) The following outline is a means for preventing the Au-An reaction. When forming a heat-resistant gate metal, an extraction electrode is formed around the ohmic electrode formation part using a heat-resistant material with the same composition as the gate metal, and the gate metal and extraction electrode are used as masks to serve as the base of the ohmic electrode in a self-aligned manner. Ion implantation of N+@. After the heat treatment step for activating the N middle layer, an Au-based ohmic metal is deposited in a lift-off step so as to overlap the edge of the ohmic region of the extraction electrode.

Next, after covering the whole thing with an insulating film, on the wiring side of the drawer electrical,
A contact hole is provided at a position that does not overlap with the ohmic metal, and is connected to the Aj-based wiring formed on the insulating film. According to this method, after forming the contact hole, 5
By being able to use most of the iVLSI wiring technology and ensuring a gap between the ohmic metal and the wiring metal on the heat-resistant extraction electrode surface,
Both reactions are completely prevented.

(Function) According to the method of the present invention, compared to the conventional method of laminating a barrier metal in the thickness direction midway between highly reactive dissimilar materials to prevent reactions between the two, pinholes and mask misalignment can be prevented. There is no risk of labor fatigue associated with this process, and there is also a high degree of freedom in selecting the heat-resistant extraction electrode material used for reaction prevention.

We also applied this method to a self-aligned heat-resistant metal gate FE.
When applied to T, S without increasing the number of processes.
In addition to being able to use the wiring technology of t, it is also possible to use circuit elements such as FETs as wiring areas, so it is comparable to the conventional technology in terms of higher density.

(Example) Hereinafter, details of the present invention will be explained with reference to the drawings, taking as an example a MESFET using a compound semiconductor GaAa as a matrix.

FIGS. 1) to 1(e) are plan views showing the manufacturing process of an embodiment of the present invention.

First, as shown in Figure 1 (&), a semi-insulating semiconductor substrate (1) is
Active II! can be formed by any method of formation, for example, by ion implantation. After forming a region Q) and depositing tungsten nitride on the entire surface, a resist pattern (not shown) is formed,
Pattern (3) is created by selectively etching the tungsten nitride pattern using a well-known etching technique.

(4m) and (4b) are formed. pap-y (4a)
(4b) does not overlap with activity II Its (2),
It is provided in a predetermined area.

Next, the 11th! ii! As shown in FIG. 1(b), using the resist pattern as a mask for ion implantation, ion implantation is performed using, for example, St ions as impurity ions to form n-medium source/drain regions (5). During C, the tungsten nitride film pattern functions as a mask for ion implantation. Thereafter, the source/drain implants are activated by a well-known heat treatment method.

Next, by a lift-off method using a resist, an insulating film, etc., an ohmic contact metal layer to GaAa having a composition of, for example, a gold-germanium alloy deposited using a vacuum evaporation method is left on the source/drain region. The regions (6a) and (6b) shown in FIG. 1 (cl) show the source and drain electrodes of the MESFET thus formed. (4a) (
4b) so that electrical contact is made. After this, the entire surface is coated with insulation 1 [(11), as shown in Fig. 1(d).
As shown in tungsten nitride film pattern (3),
Contact holes (η,
Windows (8a) and (8b) are opened in this insulating film. The insulating film is, for example, silicon oxide deposited on the entire surface by CVD, contact holes are formed by reactive ion etching using CF, gas, etc., and aluminum or aluminum alloy wiring [9], (1).
0a) and (10b) are performed to form a GaAa MESFET with self-aligned walls as shown in FIG. 1(e). FIG. 2 is a cross section taken along line A-A' of one embodiment of the present invention shown in FIGS. 1(e) and 1(f).

According to the wiring method according to this embodiment, the ohmic conductor N (6) made of Au alloy is the first @ wiring A j
(10) through the extraction electrode (4), reaction between the two is completely prevented. or.

Since AI-based wiring is used, after contact holes are formed, S
i VLS I wiring technology can be used for almost the entire time, and in this case, the extraction electrode is formed at the same time as the gate metal electrode, so there is no increase in the number of steps. For example, in addition to tungsten nitride, % TiN.

FIG. 3 shows another actual case in which, for example, the lead electrode for the source electrode side is formed integrally with the gate electrode.
Through the same process as shown in the figure, AI wiring is made through a common contact hole (12) between the gate 1 and the source electrode to obtain a load crab FET. FIG. 4 is a plan view showing a diode wiring method as a third embodiment. The positive terminal (14) of the diode and the lead-out '? After the IL pole (15) is formed of the same material as the three-dimensional key metal, the ohmic metal (16) is formed as the negative electrode of the diode through the same manufacturing process as in the first embodiment. Here, AJ-based wiring is formed through a contact hole (17) formed apart from the ohmic metal (16). The diode thus obtained can also achieve the same effect of completely preventing the reaction. Note that the number of substrates is not limited to caAs.

〔Effect of the invention〕

As described above, according to the structure of the present invention, labor fatigue due to the reaction between the ohmic electrode and the wiring material can be prevented by providing a short lead electrode on the ohmic electrode, and the high performance of the compound semiconductor device can be prevented. Reliable AI system wiring can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a top view showing the manufacturing process of an embodiment of the present invention, FIG. 2 is a sectional view of the M'FJSFET shown in FIG. FIG. 6 is a top view for explaining other embodiments of the invention. DESCRIPTION OF SYMBOLS 1... GaAs semi-insulating substrate, 2... Active layer, 3°4a, 4b, 14, 15... Tungsten nitride model, 5
...Nce Doray/@ area, 6, 6a, 6b... Ohmi V electrode, 7, 8a, 8b, 12, 17...:r
Contact hall, 9.10a, 10b, 18.19
...Aluminum or its alloy wiring. 3rd v! J Figure 4

Claims (1)

[Claims] In the wiring of compound semiconductor devices, ohmic electrodes can be formed by providing short lead electrodes on the ohmic electrodes using metal materials that do not easily react with the ohmic electrodes and wiring pattern constituent materials of the device, and connecting these to the wiring patterns. A wiring method for a compound semiconductor device characterized by preventing deterioration caused by a reaction between the wiring material and the wiring material.