JPS6295336U - - Google Patents
Info
- Publication number
- JPS6295336U JPS6295336U JP18609585U JP18609585U JPS6295336U JP S6295336 U JPS6295336 U JP S6295336U JP 18609585 U JP18609585 U JP 18609585U JP 18609585 U JP18609585 U JP 18609585U JP S6295336 U JPS6295336 U JP S6295336U
- Authority
- JP
- Japan
- Prior art keywords
- sawtooth wave
- voltage
- terminal
- modulation
- comparator circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Amplitude Modulation (AREA)
Description
第３図は従来方式のブロツク図、第２図はその
動作説明図である。第１図は本考案のブロツク図
、第４図はその動作説明図である。
１：パルス信号入力端子、２：のこぎり波発生
回路、３：のこぎり波発生回路出力、４：比較回
路、５：変調信号入力端子、６：バイアス電圧、
７：ＤＣ電圧印加端子、８：位相変調出力端子、
９：のこぎり波動作周波数ｆ０×２のパルス信号
入力端子、１０：１／２分周器、１１：１／２分
周器出力、１２：パルス発生回路２出力、１３：
サンプルホールド回路、１４：パルス発生回路１
、１５：パルス発生回路２、１６：サンプルホー
ルド回路出力、１７：加算器、１′：パルス発生
回路１出力、６′：加算器出力、Ｒ１，Ｒ２：バ
イアス電圧設定抵抗、Ｃ１：直流分除去用コンデ
ンサである。
FIG. 3 is a block diagram of the conventional system, and FIG. 2 is an explanatory diagram of its operation. FIG. 1 is a block diagram of the present invention, and FIG. 4 is an explanatory diagram of its operation. 1: Pulse signal input terminal, 2: Sawtooth wave generation circuit, 3: Sawtooth wave generation circuit output, 4: Comparison circuit, 5: Modulation signal input terminal, 6: Bias voltage,
7: DC voltage application terminal, 8: Phase modulation output terminal,
9: sawtooth wave operating frequency f 0 ×2 pulse signal input terminal, 10: 1/2 frequency divider, 11: 1/2 frequency divider output, 12: pulse generation circuit 2 output, 13:
Sample hold circuit, 14: Pulse generation circuit 1
, 15: Pulse generation circuit 2, 16: Sample hold circuit output, 17: Adder, 1': Pulse generation circuit 1 output, 6': Adder output, R 1 , R 2 : Bias voltage setting resistor, C1: DC This is a capacitor for removing components.
Claims (1)
比較回路のもう一方の端子に変調電圧を印加し、
この両入力電圧を比較することによつて位相変調
波を得る位相変調器において変調電圧のＤＣバイ
アス電圧をのこぎり波の中点電圧をサンプルホー
ルドすることにより得ることを特徴とするのこぎ
り波変調回路。 Input the sawtooth wave into one terminal of the comparator circuit,
Apply the modulation voltage to the other terminal of the comparator circuit,
A sawtooth wave modulation circuit characterized in that in a phase modulator that obtains a phase modulated wave by comparing both input voltages, a DC bias voltage of a modulation voltage is obtained by sampling and holding a midpoint voltage of the sawtooth wave.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18609585U JPS6295336U (en) | 1985-12-04 | 1985-12-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18609585U JPS6295336U (en) | 1985-12-04 | 1985-12-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6295336U true JPS6295336U (en) | 1987-06-18 |
Family
ID=31135339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18609585U Pending JPS6295336U (en) | 1985-12-04 | 1985-12-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6295336U (en) |
-
1985
- 1985-12-04 JP JP18609585U patent/JPS6295336U/ja active Pending
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