JPS6293825U - - Google Patents
Info
- Publication number
- JPS6293825U JPS6293825U JP18372185U JP18372185U JPS6293825U JP S6293825 U JPS6293825 U JP S6293825U JP 18372185 U JP18372185 U JP 18372185U JP 18372185 U JP18372185 U JP 18372185U JP S6293825 U JPS6293825 U JP S6293825U
- Authority
- JP
- Japan
- Prior art keywords
- receiving
- receiving circuit
- muting
- operated
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Noise Elimination (AREA)
Description
第1図は本考案の受信装置のブロツク図、第2
図はそのタイミングチヤート、第3図はそのフロ
ーチヤートである。
1……受信回路、3……スイツチ、4……増幅
器、5……スピーカ、6……制御手段、7……メ
モリ、8……入力手段、9……表示装置、10…
…PLL回路、11……プリスケーラ、12……
プログラマブルカウンタ、13……発振器、14
……位相比較器、15……ローパスフイルタ、8
1……プリセツト釦、82……選曲釦。
Figure 1 is a block diagram of the receiving device of the present invention;
The figure is a timing chart, and FIG. 3 is a flowchart. DESCRIPTION OF SYMBOLS 1... Receiving circuit, 3... Switch, 4... Amplifier, 5... Speaker, 6... Control means, 7... Memory, 8... Input means, 9... Display device, 10...
...PLL circuit, 11... Prescaler, 12...
Programmable counter, 13... Oscillator, 14
... Phase comparator, 15 ... Low pass filter, 8
1...Preset button, 82...Track selection button.
Claims (1)
受信回路の受信周波数を制御する制御手段と、該
受信周波数を設定するデータを記憶するメモリと
、該メモリに該データをプリセツトするプリセツ
ト手段と、該受信回路の出力をミユートするミユ
ート手段とを備える受信装置において、 該プリセツト手段を第1の所定時間以上操作し
たとき該ミユート手段により該受信回路の出力を
ミユートし、該ミユート手段により該受信回路の
出力がミユートされたときから第2の所定時間経
過した場合において該プリセツト手段が尚操作さ
れているとき、操作されている該プリセツト手段
に対応して該データを該メモリに記憶させること
を特徴とする受信装置。[Claims for Utility Model Registration] A receiving circuit that receives radio waves of a predetermined frequency, a control means that controls the receiving frequency of the receiving circuit, a memory that stores data for setting the receiving frequency, and a In a receiving device comprising presetting means for presetting data and muting means for muting the output of the receiving circuit, when the presetting means is operated for a first predetermined time or more, the muting means mutes the output of the receiving circuit. , when the preset means is still being operated after a second predetermined time period has elapsed since the output of the receiving circuit was muted by the muting means, the data is transmitted corresponding to the preset means being operated. A receiving device characterized by storing information in the memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18372185U JPH0434577Y2 (en) | 1985-11-29 | 1985-11-29 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18372185U JPH0434577Y2 (en) | 1985-11-29 | 1985-11-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6293825U true JPS6293825U (en) | 1987-06-15 |
JPH0434577Y2 JPH0434577Y2 (en) | 1992-08-18 |
Family
ID=31130719
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18372185U Expired JPH0434577Y2 (en) | 1985-11-29 | 1985-11-29 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0434577Y2 (en) |
-
1985
- 1985-11-29 JP JP18372185U patent/JPH0434577Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPH0434577Y2 (en) | 1992-08-18 |
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