JPS627098U - - Google Patents
Info
- Publication number
- JPS627098U JPS627098U JP9871785U JP9871785U JPS627098U JP S627098 U JPS627098 U JP S627098U JP 9871785 U JP9871785 U JP 9871785U JP 9871785 U JP9871785 U JP 9871785U JP S627098 U JPS627098 U JP S627098U
- Authority
- JP
- Japan
- Prior art keywords
- alarm
- week
- time
- day
- setting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Electric Clocks (AREA)
Description
第１図は実施例を示すアラーム機能付デジタル
時計の回路構成図、第２図は、第１図の各動作に
おける表示部の表示状態を示す図である。
１……発振回路、２……分周回路、３……時刻
計数回路、４……曜日計数回路、５……一致回路
、６……アラーム時刻記憶回路、１０，１８……
デコーダ／ドライバ、１１……時刻表示部、１３
……アラーム表示部、１９……曜日表示部、２０
……音符表示部、２４……メロデイ発生回路、２
５……８進カウンタ、３９……発音装置、４０…
…遅延回路、６１……時計／アラームモード切換
スイツチ、Ｓ２……アラーム設定／取消スイツチ
、Ｓ３……曜日選択スイツチ。
FIG. 1 is a circuit configuration diagram of a digital watch with an alarm function showing an embodiment, and FIG. 2 is a diagram showing the display state of the display unit in each operation of FIG. 1. DESCRIPTION OF SYMBOLS 1... Oscillation circuit, 2... Frequency division circuit, 3... Time counting circuit, 4... Day of the week counting circuit, 5... Matching circuit, 6... Alarm time storage circuit, 10, 18...
Decoder/driver, 11... Time display section, 13
...Alarm display section, 19...Day display section, 20
...Musical note display section, 24...Melody generation circuit, 2
5... Octal counter, 39... Sound generating device, 40...
...Delay circuit, 61...Clock/alarm mode selection switch, S2...Alarm setting/cancellation switch, S3...Day selection switch.
Claims (1)
ームを発生するアラーム機能を有する時計におい
て、アラーム時刻にアラームを発生させるか否か
の設定／取消を行うための入力スイツチと、この
入力スイツチの一回の操作により、全ての曜日に
ついて一括してアラームの設定／取消を行う一括
アラーム制御手段と、上記入力スイツチの操作に
より曜日別にアラームの設定／取消を行う曜日別
アラーム制御手段とを有することを特徴とするア
ラーム機能付時計。 In a watch that has an alarm function that generates an alarm every time the alarm time on the set day of the week arrives, there is an input switch for setting/cancelling whether or not to generate an alarm at the alarm time, and a one-time operation of this input switch. It is characterized by comprising a batch alarm control means for setting/cancelling alarms for all days of the week at once by operation, and a day-by-week alarm control means for setting/cancelling alarms for each day of the week by operation of the input switch. A clock with an alarm function.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9871785U JPS627098U (en) | 1985-06-28 | 1985-06-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9871785U JPS627098U (en) | 1985-06-28 | 1985-06-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS627098U true JPS627098U (en) | 1987-01-16 |
Family
ID=30966932
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9871785U Pending JPS627098U (en) | 1985-06-28 | 1985-06-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS627098U (en) |
-
1985
- 1985-06-28 JP JP9871785U patent/JPS627098U/ja active Pending
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