JPS59149738U - Receiving machine - Google Patents
Receiving machineInfo
- Publication number
- JPS59149738U JPS59149738U JP4340683U JP4340683U JPS59149738U JP S59149738 U JPS59149738 U JP S59149738U JP 4340683 U JP4340683 U JP 4340683U JP 4340683 U JP4340683 U JP 4340683U JP S59149738 U JPS59149738 U JP S59149738U
- Authority
- JP
- Japan
- Prior art keywords
- switch circuit
- output
- receiver
- mute
- unlock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Superheterodyne Receivers (AREA)
- Noise Elimination (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例の構成を示すブロック図。第
２図は本考案の一実施例の作用の説明に供する波形図。
１・・・・・・受信回路、２・・・・・・低周波増幅器
、３・・・・・・ミュートスイッチ回路、４・・・・・
・スピーカ、５・・・・・・周波数シンセサイザ、６・
・・・・・・ロータリエンコーダ、７・・・・・・分周
比制御手段、１０・・・・・・波形整形回路、１１・・
・・・・スイッチ回路、１２・・・・・・制御回路。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a waveform diagram for explaining the operation of an embodiment of the present invention. 1... Receiving circuit, 2... Low frequency amplifier, 3... Mute switch circuit, 4...
・Speaker, 5... Frequency synthesizer, 6.
... Rotary encoder, 7 ... Frequency division ratio control means, 10 ... Waveform shaping circuit, 11 ...
...Switch circuit, 12...Control circuit.
Claims (1)
しかつ局部発振器がＰＬＬ回路からなる周波数シンセサ
イザで構成されてＰＬＬ回路のアンロック信号によりミ
ュートスイッチ回路を制御してミュート動作をするよう
に構成された受信機において、前記ミュートスイッチ回
路へ供給される前記アンロック信号の遮断、非遮断を制
御するスイッチ回路と、前記選局手段が出力発生中であ
ることを検出しかつ出力により前記スイッチ回路を制御
する制御手段とを備え、前記制御手段の出力発生期間中
前記アンロック信号によるミュート動作を解除するよう
にしてなることを特徴とする受信機。It has a tuning means for setting a reception frequency by an output pulse, and the local oscillator is constituted by a frequency synthesizer consisting of a PLL circuit, and is configured to perform a mute operation by controlling a mute switch circuit by an unlock signal of the PLL circuit. In the receiver, the switch circuit controls whether the unlock signal supplied to the mute switch circuit is cut off or not, and the switch circuit detects that the tuning means is generating an output and controls the switch circuit by the output. 1. A receiver comprising: control means for controlling the receiver, and configured to release the mute operation by the unlock signal during a period in which the control means generates an output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4340683U JPS59149738U (en) | 1983-03-28 | 1983-03-28 | Receiving machine |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4340683U JPS59149738U (en) | 1983-03-28 | 1983-03-28 | Receiving machine |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59149738U true JPS59149738U (en) | 1984-10-06 |
| JPS6324677Y2 JPS6324677Y2 (en) | 1988-07-06 |
Family
ID=30173939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4340683U Granted JPS59149738U (en) | 1983-03-28 | 1983-03-28 | Receiving machine |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59149738U (en) |
-
1983
- 1983-03-28 JP JP4340683U patent/JPS59149738U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6324677Y2 (en) | 1988-07-06 |
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