JPS5978743U - display circuit - Google Patents
display circuitInfo
- Publication number
- JPS5978743U JPS5978743U JP17498882U JP17498882U JPS5978743U JP S5978743 U JPS5978743 U JP S5978743U JP 17498882 U JP17498882 U JP 17498882U JP 17498882 U JP17498882 U JP 17498882U JP S5978743 U JPS5978743 U JP S5978743U
- Authority
- JP
- Japan
- Prior art keywords
- display circuit
- utility
- manual
- activated
- response
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Circuits Of Receivers In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案の一実施例を示すブロック図である。
1・・・PLL、シンセサイザー回路、2・・・表示回
路、3・・・ディジット・ドライバ回路、5・・・電源
回路、6・・・制御回路、X、・・くニーティング出力
端子。The figure is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...PLL, synthesizer circuit, 2...Display circuit, 3...Digit driver circuit, 5...Power supply circuit, 6...Control circuit, X...Knitting output terminal.
Claims (3)
信機において、スキャン又はスイーク操作に応答して受
信周波数表示回路の表示機能を一時的に停止させる手段
を備えたことを特徴とする表示回路。(1) A display circuit in a PLL frequency synthesizer type radio receiver, comprising means for temporarily stopping the display function of the reception frequency display circuit in response to a scan or sweep operation.
らの高レベル出力によって動作するようになつn2る実
用新案登録請求の範囲第(1)項記載。 の表示回路。(2) The utility model described in claim (1), wherein the means is activated by a high-level output from a muting output terminal of a receiver. display circuit.
応じて前記手動を作動させるようにした実用新案登録請
求の範囲第(1)項記載め表示回路。(3) A display circuit according to claim (1) of the registered utility model, wherein the manual is activated in response to a fast forward operation of a manual up or down button.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17498882U JPS5978743U (en) | 1982-11-18 | 1982-11-18 | display circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17498882U JPS5978743U (en) | 1982-11-18 | 1982-11-18 | display circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5978743U true JPS5978743U (en) | 1984-05-28 |
Family
ID=30380815
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17498882U Pending JPS5978743U (en) | 1982-11-18 | 1982-11-18 | display circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5978743U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5736051B2 (en) * | 1980-06-11 | 1982-08-02 |
-
1982
- 1982-11-18 JP JP17498882U patent/JPS5978743U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5736051B2 (en) * | 1980-06-11 | 1982-08-02 |
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