JPS58178744U - Prescaler interface circuit - Google Patents

Prescaler interface circuit

Info

Publication number
JPS58178744U
JPS58178744U JP7624082U JP7624082U JPS58178744U JP S58178744 U JPS58178744 U JP S58178744U JP 7624082 U JP7624082 U JP 7624082U JP 7624082 U JP7624082 U JP 7624082U JP S58178744 U JPS58178744 U JP S58178744U
Authority
JP
Japan
Prior art keywords
prescaler
interface circuit
circuit
tuner
electronic tuning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7624082U
Other languages
Japanese (ja)
Inventor
正雄 高島
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP7624082U priority Critical patent/JPS58178744U/en
Publication of JPS58178744U publication Critical patent/JPS58178744U/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はヅンセサイザ選局回路を説明するための回路図
、第2図は上記選局回路と電子同調チューナとを結合す
る従来のプリスケーラ゛・インタフェース回路を示す回
路図、第3図は上記インターフェース回路の必要とする
周波数特性を示す特性図、第4図はチューナのAGC電
圧に対する利得、制御の一例を示すチューナAGC特性
を示す特性図、第5図は入力電界に対するチューナAG
C特性とIFAGC特性を比較して示す入力対AGC電
圧の特性図、第6図は受信チャンネルの切換えに際しチ
ューナAGC電圧が変化する様子を示すAGC電圧の変
化図、第7図は本考案の一実施例を示す回路図である。 21・・・チューナ、22・・・電圧制御発振器、26
・・・選局回路、27・・・プリスケーラ、28・・・
利得制御手段(電圧制御回路)、29・・・電源電圧供
給端子、30・・・AGC電圧給電端子、31・・・制
御信号印加端子、32・・・トランジスタ、33. 3
4゜37・・・抵抗、35・・・チューナ利得制御端子
Fig. 1 is a circuit diagram for explaining a synthesizer tuning circuit, Fig. 2 is a circuit diagram showing a conventional prescaler interface circuit that connects the above-mentioned tuning circuit and an electronic tuning tuner, and Fig. 3 is a circuit diagram showing the above-mentioned interface. A characteristic diagram showing the frequency characteristics required by the circuit. Fig. 4 is a characteristic diagram showing the tuner AGC characteristics showing an example of gain and control for the AGC voltage of the tuner. Fig. 5 is a characteristic diagram showing the tuner AGC characteristic for the input electric field.
A characteristic diagram of input vs. AGC voltage showing a comparison of C characteristics and IFAGC characteristics, FIG. 6 is a change diagram of AGC voltage showing how the tuner AGC voltage changes when switching reception channels, and FIG. FIG. 2 is a circuit diagram showing an example. 21... Tuner, 22... Voltage controlled oscillator, 26
... Tuning circuit, 27... Prescaler, 28...
Gain control means (voltage control circuit), 29... power supply voltage supply terminal, 30... AGC voltage supply terminal, 31... control signal application terminal, 32... transistor, 33. 3
4゜37...Resistor, 35...Tuner gain control terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 選局回路と電子同調チューナとをプリスケーラを用いて
結合し、局部発振周波数を正規周波数に維持するように
した制御袋−において、受信しているチャンネルの電界
が変化するような人為的操作に呼応して発生する制御信
号に基づいて前記電子同調チューナの増幅利得を制御す
る利得制御手段を設け、前記プリスケーラとこの電子同
調チ、1−ナとを結合したことを特徴とするプリスケー
ラ・インターフェース回路。
In a control bag that combines a channel selection circuit and an electronic tuning tuner using a prescaler to maintain the local oscillation frequency at a normal frequency, it is possible to respond to human operations such as changes in the electric field of the receiving channel. 1. A prescaler interface circuit comprising: a gain control means for controlling the amplification gain of said electronic tuning tuner based on a control signal generated by said prescaler;
JP7624082U 1982-05-26 1982-05-26 Prescaler interface circuit Pending JPS58178744U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7624082U JPS58178744U (en) 1982-05-26 1982-05-26 Prescaler interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7624082U JPS58178744U (en) 1982-05-26 1982-05-26 Prescaler interface circuit

Publications (1)

Publication Number Publication Date
JPS58178744U true JPS58178744U (en) 1983-11-30

Family

ID=30085562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7624082U Pending JPS58178744U (en) 1982-05-26 1982-05-26 Prescaler interface circuit

Country Status (1)

Country Link
JP (1) JPS58178744U (en)

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