JPS6241471Y2 - - Google Patents

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Publication number
JPS6241471Y2
JPS6241471Y2 JP1980178515U JP17851580U JPS6241471Y2 JP S6241471 Y2 JPS6241471 Y2 JP S6241471Y2 JP 1980178515 U JP1980178515 U JP 1980178515U JP 17851580 U JP17851580 U JP 17851580U JP S6241471 Y2 JPS6241471 Y2 JP S6241471Y2
Authority
JP
Japan
Prior art keywords
terminal
semiconductor substrate
integrated circuit
ground
prescaler
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1980178515U
Other languages
Japanese (ja)
Other versions
JPS57100344U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1980178515U priority Critical patent/JPS6241471Y2/ja
Publication of JPS57100344U publication Critical patent/JPS57100344U/ja
Application granted granted Critical
Publication of JPS6241471Y2 publication Critical patent/JPS6241471Y2/ja
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 本考案は、モノリシツク又はハイブリツド集積
回路等の回路ブロツクに係り、特に複数の回路ブ
ロツク中、1集積回路の使用、不使用に応じて電
源ラインを制御する集積回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to circuit blocks such as monolithic or hybrid integrated circuits, and particularly to an integrated circuit that controls a power supply line depending on whether one integrated circuit among a plurality of circuit blocks is used or not.

一般に複数の集積回路(以下ICと称する)を
組合せて構成されるラジオ受信機において例えば
FMバンドとAMバンドを備えている場合、PLL
(Phase Locked Loop位相ロツクトループ)方式
を採用したICと他のブロツクのICを組合せると
き、特にプリスケーラ用ICは、FM受信時その構
成要素として必要であるが、AM受信時は不要で
あり、このとき電源のVCCラインを接続したまま
では、電力消費を生じ、電池駆動の場合、ロスと
なり該電池が消耗するばかりでなく、不要輻射の
原因ともなつていた。従つてAM受信時の電力消
費を減らすために、本考案は前記半導体基板7と
接地端子16との間にスイツチング素子8を接続
し、AM受信時にはスイツチング素子を制御する
制御端子17に制御信号を印加して半導体基板7
と接地端子16間の電流路を切断する。一方FM
受信時にはプリスケーラ用ICを動作させるため
にスイツチング素子であるトランジスタ8は、前
記制御端子17を介して立上り電圧以上の電圧が
与えられてオン状態となり、前記半導体基板7は
ほぼ接地電位となる。
In a radio receiver that is generally constructed by combining multiple integrated circuits (hereinafter referred to as IC), for example,
PLL if equipped with FM and AM bands
When combining an IC that adopts the (Phase Locked Loop) method with another block's IC, a prescaler IC is especially necessary as a component when receiving FM, but it is not necessary when receiving AM. If the V CC line of the power source is left connected, power consumption occurs, and in the case of battery drive, not only is there a loss and the battery is consumed, but it is also a cause of unnecessary radiation. Therefore, in order to reduce power consumption during AM reception, the present invention connects a switching element 8 between the semiconductor substrate 7 and the ground terminal 16, and sends a control signal to a control terminal 17 that controls the switching element during AM reception. Applying voltage to the semiconductor substrate 7
and the ground terminal 16. On the other hand, FM
During reception, in order to operate the prescaler IC, the transistor 8, which is a switching element, is applied with a voltage higher than the rising voltage via the control terminal 17 to be turned on, and the semiconductor substrate 7 becomes approximately at ground potential.

しかし、前記トランジスタ8のコレクタ・エミ
ツタ間電圧VCEだけ前記半導体基板7がシフトし
てしまい、入力端子13,14に交流信号を入力
すると、出力信号はVCEとVCC間でスイングし、
プリスケーラ用ICとPLL回路11とのレベルマ
ツチングができない問題点を有していた。
However, the semiconductor substrate 7 shifts by the collector-emitter voltage V CE of the transistor 8, and when an AC signal is input to the input terminals 13 and 14, the output signal swings between V CE and V CC .
There was a problem in that level matching between the prescaler IC and the PLL circuit 11 could not be performed.

そこで本考案は前述の欠点を除去した新規な集
積回路を提供するものである。以下図面に従つて
説明すると、1はバツフアアンプ2,3、分周器
4,5,6、半導体基板サブストレート7、スイ
ツチングトランジスタ8及びバイアス抵抗9,1
0を有するプリスケーラ用IC、11はPLL用
IC、21は交流的に前記半導体基板7を接地す
るためのコンデンサを示す。
The present invention therefore provides a novel integrated circuit which eliminates the above-mentioned drawbacks. Referring to the drawings, 1 includes buffer amplifiers 2, 3, frequency dividers 4, 5, 6, semiconductor substrate 7, switching transistor 8, and bias resistors 9, 1.
0 for prescaler IC, 11 for PLL
IC 21 represents a capacitor for grounding the semiconductor substrate 7 in an alternating current manner.

前記IC1は電源VCC端子12、入力端子1
3,14、基板端子15、接地端子16、制御端
子17、出力端子18を有している。
The IC1 has a power supply V CC terminal 12 and an input terminal 1.
3, 14, a substrate terminal 15, a ground terminal 16, a control terminal 17, and an output terminal 18.

次に前記プリスケーラ用IC1を使用する場合
即ちFM受信時には、PLL用IC11から制御信号
Cが端子19から導出される。この制御信号は
スイツチングトランジスタ8の立上り電圧以上に
なつており、該スイツチングトランジスタ8はオ
ン即ちサブストレートは接地電位になつており、
電源電圧VCCにより、入力信号Viは1/25分周さ
れ、出力電圧V0は出力端子18から導出され、
前記バツフアアンプ2,3及び分周器4,5,6
は通常動作を行う。この場合接地用コンデンサ2
1は交流分接地用として働く。ここで接地用コン
デンサ21は前述の如く前記半導体基板7を交流
的に接地されてあるので、交流信号がプリスケー
ラ用ICの入力に印加された時に、半導体基板7
からトランジスタ8を介して流れていた交流信号
は、コンデンサ21でバイパスされる。そのため
トランジスタ8の動作により引上げられた電圧V
CEは交流的に接地電圧まで引き下げられるため出
力電圧はOVからVCCの間でフルスイングする。
Next, when the prescaler IC 1 is used, that is, during FM reception, the control signal Vc is output from the PLL IC 11 through the terminal 19. This control signal is equal to or higher than the rising voltage of the switching transistor 8, and the switching transistor 8 is on, that is, the substrate is at the ground potential.
The input signal Vi is divided by 25 by the power supply voltage V CC , and the output voltage V 0 is derived from the output terminal 18 .
The buffer amplifiers 2, 3 and the frequency dividers 4, 5, 6
In this case, the grounding capacitor 2 operates normally.
Here, the grounding capacitor 21 serves as an AC ground for the semiconductor substrate 7, as described above, so that when an AC signal is applied to the input of the prescaler IC, the semiconductor substrate 7 is
The AC signal flowing from the transistor 8 is bypassed by the capacitor 21. Therefore, the voltage V
Since CE is AC pulled down to ground, the output voltage will swing fully between OV and V CC .

従つて高周波の出力波形はフルスイングするた
めに、前記出力端子18と高周波用ICである外
部接続回路(例えばPLL回路11)とのレベルマ
ツチングが良好となる。
Therefore, since the high frequency output waveform has a full swing, the level matching between the output terminal 18 and the external connection circuit (for example, the PLL circuit 11) which is a high frequency IC becomes good.

一方前記プリスケーラ用IC1の不使用時、即
ちAM受信時には、PLL用IC11の端子19から
の制御信号VCはゼロであるから、スイツチング
トランジスタ8はオフになつて、前記バツフアア
ンプ2,3及び分周器4,5,6には付勢電流が
流れないので不動作状態となつて、図示の例では
PLL用IC11に電源電圧VCCが端子20に加わ
るのみで、種々端子(図示せず)から所定の信号
が入力信号に応じて、導出されAM受信動作を行
う。
On the other hand, when the prescaler IC 1 is not used, that is, during AM reception, the control signal V C from the terminal 19 of the PLL IC 11 is zero, so the switching transistor 8 is turned off and the buffer amplifiers 2, 3 and Since no energizing current flows through the frequency dividers 4, 5, and 6, they become inoperative, and in the illustrated example,
By simply applying the power supply voltage V CC to the terminal 20 of the PLL IC 11 , predetermined signals are derived from various terminals (not shown) according to the input signals to perform the AM reception operation.

以上の通り本考案によれば、複数の回路ブロツ
クの中で、1の集積回路を目的に応じて動作、不
動作状態に切換えるときに、該集積回路の基板電
位を制御することによつて付勢電流を接断するこ
とができ、電池駆動の電子機器の電流消耗を軽減
でき、更に前記集積回路の不動作時従来生じてい
た不要輻射等の障害も完全に除去できる利点が得
られる。更にはコンデンサ21を基板端子15と
接地間に接続して交流的に前記半導体基板7を接
地させるために高周波の出力波形はOVからVCC
の間でフルスイングをし、前記出力端子18と外
部接続回路11とのレベルマツチングが良好とな
る。
As described above, according to the present invention, when one integrated circuit among a plurality of circuit blocks is switched into an active state or a non-active state according to the purpose, the substrate potential of the integrated circuit is controlled. It is possible to cut off the power current, reduce current consumption in battery-powered electronic equipment, and furthermore, it is possible to completely eliminate disturbances such as unnecessary radiation that conventionally occur when the integrated circuit is not in operation. Furthermore, in order to connect the capacitor 21 between the board terminal 15 and the ground to ground the semiconductor board 7 in an alternating current manner, the high frequency output waveform changes from OV to V CC
The level matching between the output terminal 18 and the external connection circuit 11 is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案の集積回路の一実施例を示す。 主な図番の説明、1……プリスケーラ用IC、
7……半導体基板、11……PLL用IC、15…
…基板端子、16……接地端子、17……制御端
子。
The drawing shows an embodiment of the integrated circuit of the present invention. Explanation of main drawing numbers, 1... prescaler IC,
7...Semiconductor substrate, 11 ...IC for PLL, 15...
... Board terminal, 16 ... Ground terminal, 17 ... Control terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の構成要素を含む集積回路に於いて、該構
成要素の一電源供給端と共通に接続される半導体
基板と、該半導体基板と接続されかつ外部の接地
電位に一端が接続されたコンデンサの他端を接続
するための基板端子と、前記外部の接地電位と接
続するための接地端子と、該接地端子と前記半導
体基板との間に接続されるスイツチング素子と、
該スイツチング素子を制御する制御端子とを備え
ることを特徴とした集積回路。
In an integrated circuit including a plurality of components, a semiconductor substrate is commonly connected to one power supply terminal of the components, and a capacitor is connected to the semiconductor substrate and has one end connected to an external ground potential. a substrate terminal for connecting the ends, a ground terminal for connecting to the external ground potential, and a switching element connected between the ground terminal and the semiconductor substrate;
An integrated circuit comprising: a control terminal for controlling the switching element.
JP1980178515U 1980-12-11 1980-12-11 Expired JPS6241471Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1980178515U JPS6241471Y2 (en) 1980-12-11 1980-12-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1980178515U JPS6241471Y2 (en) 1980-12-11 1980-12-11

Publications (2)

Publication Number Publication Date
JPS57100344U JPS57100344U (en) 1982-06-21
JPS6241471Y2 true JPS6241471Y2 (en) 1987-10-23

Family

ID=29973380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1980178515U Expired JPS6241471Y2 (en) 1980-12-11 1980-12-11

Country Status (1)

Country Link
JP (1) JPS6241471Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5360188A (en) * 1976-11-10 1978-05-30 Epson Corp Ic for electronic device having complex functions
JPS5427785A (en) * 1977-08-04 1979-03-02 Nec Corp Integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5360188A (en) * 1976-11-10 1978-05-30 Epson Corp Ic for electronic device having complex functions
JPS5427785A (en) * 1977-08-04 1979-03-02 Nec Corp Integrated circuit

Also Published As

Publication number Publication date
JPS57100344U (en) 1982-06-21

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