JP2866843B1 - FHSS wireless LAN transceiver - Google Patents

Abstract

A PLL circuit can be shared between two local oscillation circuits, the number of components is reduced, and the space occupied by components is reduced. In a FHSS wireless LAN transceiver, a PLL circuit (23A) used by a first local oscillation circuit (21).
Is switched to the second local oscillation circuit 31 by a switching signal output from the modem 16 when the transmission / reception sleep mode is set. Then, the sample hold circuit 35 provided in the second local oscillation circuit 31 is set to the sample mode to correct the oscillation frequency, and when returning to the transmission / reception mode, the PLL circuit 23A is switched to the first local oscillation circuit 21 side. ,
The sample and hold circuit 35 of the second local oscillation circuit 31 is set to the hold mode to keep the frequency control voltage Vvco2 constant.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FHSS wireless LAN transceiver having two local oscillation circuits.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional FHSS (frequency hopping spread spectrum) wireless LAN transceiver. In FIG. 6, RF is a high frequency amplifier, IF1 is a first intermediate frequency amplifier, and IF2 is a second intermediate frequency amplifier.

In the high-frequency amplifier RF, 1 is a receiving (Rx) antenna, and a signal received by the receiving antenna 1 is a receiving amplifier (Rx-LNA: low noise amplifier).
The signal is input to the first mixer 4 via the second high-frequency branch circuit 3. A transmission signal input from the first mixer 4 to the high-frequency branch circuit 3 is sent to a transmission antenna 6 via a transmission amplifier (Tx-HPA: high power amplifier) 5.

The first mixer 4 includes a first intermediate frequency amplifier IF comprising a first branch circuit 7, a reception intermediate frequency amplifier 8, a transmission intermediate frequency amplifier 9, and a second branch circuit 10.
1 is connected.

The second branch circuit 10 includes a second mixer 11
, A second intermediate frequency amplifier IF including a branch circuit 12, a reception intermediate frequency amplifier 13, and a transmission intermediate frequency amplifier 14.
2 is connected.

The output signal of the receiving intermediate frequency amplifier 13 is converted into a digital signal by an A / D converter 15 and sent to a modem 16. The transmission signal output from the modem 16 is sent to the transmission intermediate frequency amplifier 14 via the D / A converter 17. The modem 16 is connected to a personal computer (not shown), not shown.

The first mixer 4 receives a local oscillation signal from a first local oscillation circuit (frequency hopping) 21. The first local oscillation circuit 21 includes a phase-locked oscillator including a first voltage-controlled oscillator (VCO) 22, a PLL circuit 23, and a low-pass filter 24. The reference frequency signal output from the reference oscillator 25 is divided into two. The signal is input to the PLL circuit 23 via the device 26.

The second mixer 11 receives a local oscillation signal from a second local oscillation circuit (fixed frequency) 31. The second local oscillation circuit 31 includes a phase-locked oscillator including a second voltage-controlled oscillator (VCO) 32, a PLL circuit 33, and a low-pass filter 34. The reference frequency signal output from the reference oscillator 25 is divided into two. The signal is input to the PLL circuit 33 via the device 26. The PLL circuit 23 and P
The LL circuit 33 receives frequency division ratio data sent from the personal computer via the modem 16.

[0009]

In the above-mentioned conventional FHSS wireless LAN transceiver, focusing on the frequency converter, the first local oscillation circuit 21 for performing frequency hopping and the second local oscillation circuit 31 having a fixed frequency have the same configuration. It can be seen that two exist. Both oscillation circuits 21 and 31 are PLL
Although the circuits 23 and 33 are used to stabilize the frequency, PLL circuits are provided for the respective oscillation circuits, so that disadvantages such as an increase in the number of parts and an increase in the space occupied by the parts have occurred. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an FHS capable of sharing a PLL circuit, reducing the number of components and reducing the space occupied by components.
An object of the present invention is to provide an S wireless LAN transceiver.

[0011]

According to the present invention, there is provided an FHSS wireless LAN transceiver including a first local oscillation circuit for performing frequency hopping and a second local oscillation circuit for fixed frequency, each comprising a phase locked oscillator. A PLL circuit shared by the first local oscillation circuit and the second local oscillation circuit;
When the switching signal output according to the operation mode of the FHSS wireless LAN transceiver is other than the transmission / reception sleep mode, the PLL circuit is connected to the first local oscillation circuit by switching, and when the switching signal is the transmission / reception sleep mode, A switching circuit for switching and connecting a PLL circuit to the second local oscillation circuit;
A sample-and-hold circuit provided in the second local oscillation circuit, and an oscillation frequency is corrected by setting the sample-and-hold circuit to the sample mode when the PLL circuit is switched to the second local oscillation circuit in the transmission / reception sleep mode. And a means for setting the sample-and-hold circuit to the hold mode and holding the frequency control voltage constant when the switching signal is switched to a mode other than the transmission / reception sleep mode.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an FHSS (frequency hopping spread spectrum) wireless LAN transceiver according to an embodiment of the present invention.

In the present invention, as shown in FIG. 1, the configuration of the first local oscillation circuit 21 and the second local oscillation circuit 31 is different from that of the conventional device shown in FIG. Therefore, the same portions are denoted by the same reference numerals, and detailed description is omitted.

In the conventional device, PLL circuits are provided in the first local oscillation circuit 21 and the second local oscillation circuit 31, respectively. However, in the present invention, the first local oscillation circuit 21 and the second local oscillation circuit 31 One PLL circuit 23A is switched and used.

The PLL circuit 23A receives the signal of the reference frequency from the reference oscillator 25 and the frequency division ratio data from the personal computer connected to the modem 16 via the modem 16. Then, the PLL circuit 23A
The first voltage-controlled oscillator 22 of the first local oscillation circuit 21 and the low-pass filter 2
4 or a second voltage controlled oscillator 32 of the second local oscillation circuit 31 and a low-pass filter 34. A signal for switching various operation modes is output from the modem 16, and a power on / off signal of a transmission (Tx) circuit and a reception (Rx) circuit in the signal is taken out via an OR circuit and switched. This is a switching signal for the switches 41 and 42. When the FHSS wireless LAN transceiver shifts to the transmission / reception sleep operation, the logic levels of the power on / off signals of the transmission (Tx) circuit and the reception (Rx) circuit both become “L” level.

In the first local oscillation circuit 21, the first voltage controlled oscillator 22 and the low-pass filter 24 are directly connected, but in the second local oscillation circuit 31, the second voltage controlled oscillator 32 A sample hold circuit 35 is provided between the filter and the band-pass filter 34. The sample-and-hold circuit 35 uses a switching signal output from the modem 16
The operation mode is switched.

Since the second local oscillation circuit 31 has a fixed local oscillation frequency, it is sufficient to apply temporary correction periodically. For this reason, the PLL circuit 23A used by the first local oscillation circuit 21 is borrowed and connected to the second local oscillation circuit 31 for correction, and the second voltage controlled oscillator 32
Is sampled and held by the sample-and-hold circuit 35, and then the PLL circuit 23A is reconnected to the first local oscillation circuit 21 to obtain a signal between the two local oscillation circuits 21 and 31. 1
The sharing of the PLL circuit 23A is realized.

The PLL circuit 23A, which is a common part of the two local oscillation circuits 21 and 31, is connected to the first local oscillation circuit 21 for a relatively long time. However, when the frequency of the second local oscillation circuit 31 is corrected, the PLL circuit 23A
It is connected to the local oscillation circuit 31, during which the first local oscillation circuit 21 is unlocked. Therefore, the frequency correction of the second local oscillation circuit 31 needs to be performed in the wireless LAN transceiver using a time zone in which RF, IF1, and IF2 are not used.

The operation state of the wireless LAN transceiver is roughly divided into three modes: (1) transmission / reception sleep (2) carrier sense (3) frame transmission / reception. Since RF, IF1 and IF2 are not used only in the operation mode (1), the frequency of the second local oscillation circuit 31 is corrected using this time zone.

The frequency correction process is performed according to the flowchart shown in FIG. When the operation mode becomes the transmission / reception sleep mode and the power supplies of the Tx (transmission) system and the Rx (reception) system are both turned off, the switching signal is switched from the “H” level to the “L” level. Changeover switches 41, 4
2, the switching signal determines whether the powers of the Tx (transmission) system and the Rx (reception) system are both turned off (step A1). If both the power supplies are turned off and the switching signal is at the “L” level, the operation mode is the transmission / reception sleep mode.
The PLL circuit 23A is connected to the second local oscillation circuit 31 (Step A2). Next, the frequency division ratio data output from the modem 16 is input to the PLL circuit 23A, and the frequency division ratio is set to a value suitable for the second local oscillation circuit 31 (step A3). Further, the sample hold circuit 35 enters the sample mode (step A4). In this state, a PLL loop is formed in the second local oscillation circuit 31, and when the frequency is locked, the control voltage converges to a constant value.

Thereafter, when the power of the Tx (transmission) system or the Rx (reception) system is turned on, the switching signal goes to the "H" level, and the sample / hold circuit 35 enters the hold mode (step A5). Hold voltage. When the switching signal becomes “H” level,
The changeover switches 41 and 42 are switched, and the PLL circuit 23A
Is connected to the first local oscillation circuit 21 (step A6), and the process returns to step A1. As described above, in the transmission / reception sleep operation mode, the frequency correction processing of the second local oscillation circuit 31 is performed.

Next, a specific circuit configuration of the present invention will be described. FIG. 3 shows the overall circuit configuration. On / off signals of the power supply to the transmission circuit and the reception circuit output from the modem 16 are taken out via the OR circuit 36, and are switched as switching signals by the switching circuit 43 and the switching circuit 43. The signal is input to the sample and hold circuit 35. The switching circuit 43 corresponds to the circuit shown in FIG.
Corresponds to the changeover switches 41 and 42 in FIG.

As shown in detail in FIG. 4, the switching circuit 43 includes a switching signal input terminal 51, a first VCO connection terminal 52,
A second VCO connection terminal 53 and a PLL connection terminal 54 are provided. The first VCO connection terminal 52 is connected to the capacitor C1
Is connected to the anode of the PIN diode D1 through
The second VCO connection terminal 53 is connected to the PI via the capacitor C2.
Connected to the anode of N diode D2. The above PIN
The switching signal input terminal 5 is connected to the anode side of the diode D1.
1 is provided as a bias signal via a resistor R1 and a coil L1, and the switching signal is supplied to the anode side of the PIN diode D2.
5, is supplied as a bias signal via the resistor R1 and the coil L2. Then, the PIN diodes D1, D
The two cathodes are collectively connected, grounded via a coil L3, and connected to a PLL connection terminal 54 via a capacitor C3.

The switching circuit 43 configured as described above
When the switching signal is at "H" level, the PIN diode D1 is turned on and the PIN diode D2 is turned on as shown in FIG.
Is turned off. In this case, the first VCO connection terminal 52
Is input from the first voltage controlled oscillator 22 to PI
The signal is sent to the PLL circuit 23A via the N diode D1.

When the switching signal is at the "L" level, the output of the inverter 55 goes to the "H" level as shown in FIG. 4B, turning on the PIN diode D2 and turning off the PIN diode D1. In this case, the signal from the second voltage controlled oscillator 32 input to the second VCO connection terminal 53 is transmitted to the PLL circuit 23A via the PIN diode D2.
Sent to

The sample-and-hold circuit 35 is provided as shown in FIG.
As shown in (1), buffer amplifiers 61 and 62, a first FET switch 63, and a second FET switch 64 are provided. The output signal of the low-pass filter 34 is amplified by the buffer amplifier 61 and input to the buffer amplifier 62 via the first FET switch 63. The output voltage Vvco2 of the buffer amplifier 62 is input to the second voltage controlled oscillator 32.

The drain of the first FET switch 63 has:
A signal output from the inverter 55 of the changeover switch 41 is input via a resistor. First FET switch 6
3 has a source connected to the buffer amplifier 62 and grounded via a capacitor C4, a drain connected to the buffer amplifier 61 and grounded via a resistor R3. The switching signal output from the OR circuit 36 is input to the gate of the second FET switch 64 via a resistor. The output signal of the inverter 55 is input to the source of the second FET switch 64, and the drain is grounded.

FIGS. 5A and 5B show an equivalent circuit of the sample and hold circuit 35. A first FET switch 63 is provided between a buffer amplifier 61 and a buffer amplifier 62. , A resistor R3 is connected between the output terminal and the ground, and a capacitor C4 is provided between the input terminal of the buffer amplifier 62 and the ground. Then, the signal output from the low-pass filter 34 is input to the buffer amplifier 61 via the terminal 65, and the output voltage Vvco2 of the buffer amplifier 62 is sent to the second voltage controlled oscillator 32 via the terminal 66.

In the above configuration, the FHSS wireless LAN
When the transceiver is in the normal transmission / reception mode, that is, in the mode of carrier sense or frame transmission / reception, the switching signal output from the modem 16 via the OR circuit 36 is at the “H” level. Switching signal is "H"
In the case of the level, the switching circuit 43 turns on the pin diode D1 and turns off the pin diode D2 as shown in FIG. 4A, and the PLL circuit 23A is connected to the first voltage-controlled oscillator 22 of the first local oscillation circuit 21 with the low level. Connected between the low-pass filter 24 and the output voltage Vvco
2 controls the oscillation operation of the first voltage controlled oscillator 22.

When the FHSS wireless LAN transceiver enters the transmission / reception sleep operation mode and the switching signal output from the modem 16 via the OR circuit 36 becomes "L" level, the switching circuit 43 switches to the state shown in FIG. , The output of the inverter 55 becomes "H" level, the pin diode D2 turns on, the pin diode D1 turns off, and the PLL
The circuit 23A is connected between the second voltage controlled oscillator 32 of the second local oscillation circuit 31 and the low-pass filter 34. Then, the PLL circuit 23 </ b> A is set to a frequency division ratio corresponding to the second local oscillation circuit 31 based on the frequency division ratio data provided from the modem 16.

Further, as described above, the sample-and-hold circuit 35 switches the inverter 5
When the signal of the "H" level is output from 5, the first FET switch 63 is turned on as shown in FIG. At this time, the switching signal input to the gate of the second FET switch 64 is “L”.
The level is off because of the level.

In the above sample mode, the second local oscillation circuit 31 forms a PLL loop. When the frequency is locked, a predetermined charge is stored in the capacitor C4, and the frequency control voltage output from the buffer amplifier 62 is output. Vvc
o2 converges to a constant value.

Thereafter, when the FHSS wireless LAN transceiver enters the transmission / reception mode and the switching signal output from the modem 16 via the OR circuit 36 attains the "H" level, the output of the inverter 55 attains the "L" level. As shown in (b), the first FET switch 63 of the sample and hold circuit 35 is turned off, and the apparatus enters the hold mode. When the first FET switch 63 is turned off, the capacitor C4 is disconnected from the buffer amplifier 62 and the resistor R3, and keeps the voltage immediately before the first FET switch 63 was turned off without discharging the stored charge. As a result, the second local oscillation circuit 31 is locked at a desired frequency defined by the frequency division ratio data output from the modem 16.

The sample-and-hold circuit 35 includes:
At the same time when the switching signal is switched to "H" level, the second F
The ET switch 64 is turned on, and the first FET switch 6
3 is connected to the ground line (GND), thereby increasing the off response of the first FET switch 63. Thus, the sample and hold circuit 35 is shifted to the hold mode before the switching circuit 43 is switched, and
The frequency control voltage Vvco2 is securely held.

On the other hand, when the switching signal is switched to the "H" level, the switching circuit 43 turns on the pin diode D1 and turns off the pin diode D2, as shown in FIG. Again, the first local oscillation circuit 21
Connected to the side. Then, the PLL circuit 23A is set to a frequency division ratio corresponding to the first local oscillation circuit 21 based on the frequency division ratio data sent from the modem 16. Thereby, the transmission / reception operation of the FHSS wireless LAN transceiver can be performed normally.

[0036]

As described above in detail, according to the present invention, F
In the HSS wireless LAN transceiver, the PLL circuit used by the first local oscillation circuit is switched to the second local oscillation circuit when the transmission / reception sleep mode is set, and the sample-and-hold circuit provided in the second local oscillation circuit is switched. The oscillation frequency is corrected by setting to the sample mode, and when returning to the transmission / reception mode, the PLL circuit is switched to the first local oscillation circuit side, and the sample and hold circuit of the second local oscillation circuit is set to the hold mode to set the frequency. Since the control voltage is held, the PLL circuit can be shared between the two local oscillation circuits, the number of components can be reduced, and the space occupied by the components can be reduced.

[Brief description of the drawings]

FIG. 1 is an FHSS wireless LAN according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a transceiver.

FIG. 2 is a flowchart showing a processing operation in the embodiment.

FIG. 3 is an overall circuit configuration diagram showing a specific configuration of the present invention.

FIG. 4 is an exemplary view for explaining a switching operation of the switching circuit in the embodiment.

FIG. 5 is an equivalent circuit diagram for explaining the operation of the sample and hold circuit in the embodiment.

FIG. 6 is a block diagram showing a configuration of a conventional FHSS wireless LAN transceiver.

[Explanation of symbols]

 4 First Mixer 11 Second Mixer 16 Modem 21 First Local Oscillator 22 First Voltage Controlled Oscillator 23, 23A PLL Circuit 24 Low Pass Filter 25 Reference Oscillator 26 2 Divider 31 Second Local Oscillator 32 Second Voltage Control Oscillator 33 PLL circuit 34 Low-pass filter 35 Sample and hold circuit 41, 42 Switch 43 Switch 61, 62 Buffer amplifier 63 First FET switch 64 Second FET switch

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04B 1/713 H04B 1/40

Claims (1)

(57) [Claims] 1. An FHSS wireless LAN transceiver comprising a first local oscillation circuit for performing frequency hopping and a second local oscillation circuit having a fixed frequency, each comprising a phase-locked oscillator, wherein the first local oscillation circuit and the second local oscillation circuit are provided. A PLL circuit shared by the oscillation circuit, and a switching signal output according to an operation mode of the FHSS wireless LAN transceiver other than the transmission / reception sleep mode, the PLL circuit being switched and connected to the first local oscillation circuit, A switching circuit for switching and connecting the PLL circuit to the second local oscillation circuit when the switching signal is in the transmission / reception sleep mode; a sample / hold circuit provided in the second local oscillation circuit; and the PLL circuit in the transmission / reception sleep mode Is the second
Correction means for setting the sample hold circuit to the sample mode when switched to the local oscillator circuit and correcting the oscillation frequency; and holding the sample hold circuit when the switch signal is switched to a mode other than the transmission / reception sleep mode. Means for setting a mode to keep the frequency control voltage constant.