JP2002009653A - Integrated circuit for wireless unit, and wireless phone with the integrated circuit mounted thereon - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit for a wireless unit, the number of the signal lines of which is reduced, and to provide a wireless phone having the integrated circuit mounted thereon. SOLUTION: In the integrated circuit IC 20, provided with a PLL IC 6 for configuring part of a frequency synthesizer circuit, a limiter circuit 16 that configures a part of a reception circuit, and a 2nd mixer 14, a transistor(TR) switch 19 is connected between a signal line for an RSSI signal (2) and a ground. At the detection of out of synchronism of the frequency synthesizer circuit, a synchronization detecting signal (1) goes to L level, and the TR switch 19 is closed to forcibly fix the RSSI signal (2) to 0 V. Thus, the signal line of the RSSI signal (2) is used in common with the signal line for the synchronization detection signal (1), and signal line can be reduced by one.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio integrated circuit in which at least an integrated circuit for a frequency synthesizer and an integrated circuit for reception are integrated, and a radio telephone device equipped with the integrated circuit.

[0002]

2. Description of the Related Art A frequency synthesizer circuit in a conventional radio has been configured as shown in FIG. In the frequency synthesizer circuit shown in FIG. 2, the output of the reference signal oscillator 1 is input to the phase comparator 2. The phase comparator 2 detects a phase error between a signal obtained by dividing an output signal of a voltage controlled oscillator (hereinafter referred to as VCO) 4 by a variable frequency divider 5 having a frequency division number N and a reference signal. The detected phase error signal is smoothed to a DC component through a low-pass filter (hereinafter, LPF) 3,
It is fed back to CO4. As a result, the output frequency of the VCO 4 is locked at N times the reference signal.

[0003] Among these circuits, LPF3, VCO4,
Since the circuit can be constituted by a digital circuit except for the reference oscillator 1, the part 6 shown in FIG. 2 is formed into an IC (integrated circuit) to constitute an IC for a frequency synthesizer, and the circuit is downsized. In a state where the frequency synthesizer circuit is not synchronized in the wireless device, not only cannot the signal be received, but if the signal is transmitted, the other users will be troubled. Therefore, the normal frequency synthesizer IC 6 is provided with a synchronization detection circuit for detecting whether or not the synchronization is established, and the CP for controlling the radio is provided.
It is configured to output a signal for causing U or the like to recognize, that is, an out-of-synchronization detection signal.

FIG. 3 shows an example of the synchronization detecting circuit. This is a block diagram showing the logical configuration of the phase comparator 2. This circuit has two inputs: input 1A, input 2
B, the phase difference is detected, and a correction pulse for controlling the VCO is output from the terminal C as a phase comparator output.
This operation will be described with reference to the timing chart shown in FIG. Initially, two D flip-flops (D
-FF) is in a reset state. Here, when a pulse is applied to one input (for example, input 1), the output of the D-FF (for example, output Q1 of D-FF1) becomes H, and an H signal is output as a phase comparator output.

Next, when a pulse is applied to the other input (for example, input 2), the output of D-FF (for example, D-FF2
Output Q2) becomes H, and the output of the AND gate becomes H, which is applied as a reset signal to generate two DFs.
Since F is reset, the phase comparator output goes into a high impedance state.

As described above, an H or L pulse is output as a phase comparator output for a time corresponding to the phase difference between two input pulses. Here, if an OR gate is inserted in parallel with the AND gate, a signal in which an H pulse is output only for a time corresponding to the phase error, that is, a phase error signal can be generated. The state where the phase error is stable at a very small value is synchronized, and when the pulse width is large, the state is not synchronized.

However, since it is difficult for the CPU to determine whether or not the synchronization is performed as it is, a pulse width detection circuit for detecting whether or not the pulse width exceeds a predetermined value is added. Is output. In order to detect the pulse width, a reference signal applied to the frequency synthesizer IC (PLL IC) 6 is used.

Next, FIG. 5 shows a circuit configuration of the receiver. This is a normal double superheterodyne receiver, in which an output signal of the above-described frequency synthesizer is applied to a first local oscillator. Here, a receiver such as a wireless telephone device such as a mobile phone has a function of displaying the received electric field strength, that is, a function of outputting an RSSI signal, which is integrated into a limiter circuit in a receiving unit. It is configured. This RSSI signal generally has a detection characteristic that increases in proportion to an increase in the reception electric field.

[0009] When further miniaturization is required, such as in a cellular phone, the frequency synthesizer IC is further integrated with other circuits. FIG. 6 shows a configuration of a wireless device in a mobile phone.

[0010] IC for frequency synthesizer in FIG.
(PLL IC) 6 is represented as PLL 6 in FIG. The signal of the PLL 6 is split into two, and one is input to the quadrature modulator (QMOD) 21. The quadrature modulator 21 modulates the output signal of the PLL 6 with the transmission IQ signal,
Bandpass filter (hereinafter BPF) 2 for removing unnecessary waves
2, a variable gain amplifier 23 for adjusting to an appropriate level, a power amplifier (hereinafter, PA) 24 for amplifying power required for speech,
Radiation is radiated from the antenna 7 via an isolator 25 for stabilizing the load of the PA and an antenna duplexer (hereinafter referred to as DUP) 8.

On the other hand, for reception, a signal received by the antenna 7 is applied to the first mixer 12 via the DUP 8, the BPF 9 for removing spurious signals, the amplifier 10, and the BPF 11. The first mixer 12 mixes the received signal with the output signal of the VCO controlled by the PLL 6, and obtains a first intermediate frequency signal (hereinafter, 1stIF). After passing through the filter 13, the first IF is applied to the second mixer 14 and mixed with the output signal of the second VCO controlled by the PLL 6 to obtain a second intermediate frequency signal (hereinafter, 2ndIF). 2nd IF is filter 1
5. After the signal is amplified to a level sufficient for demodulation by the limiter circuit 16, it operates to extract the received information by a detection circuit (not shown).

Further, the PLL 6 outputs a synchronization detection signal indicating whether or not the frequency synthesizer circuits are synchronized.

Further, the limiter circuit 16 has a function of detecting the received signal, wherein the RS
SI (Received Signal Strong)
thIndicator: RSSI) signal is generated.

Block 2 shown by a dashed line in FIG.
Numeral 0 is a part that can be integrally formed by IC. That is, FIG.
In the above, the PLL 6 forming a part of the frequency synthesizer circuit, the second mixer 14 and the limiter circuit 16 forming a part of the receiving circuit, the quadrature modulator forming a part of the transmitting circuit, and the distributor are integrated. Thus, one IC 20 is provided. In this case, the number of signal lines required for controlling and monitoring the wireless device becomes considerably large, and a problem arises in that wiring becomes difficult when designing a board.

[0015]

As described above, in the above-described device, the number of signal lines connecting the control unit and the radio unit is increased, and there is a problem that restricts high-density mounting.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a radio integrated circuit with a reduced number of signal lines and a radio telephone device equipped with the integrated circuit. And

[0017]

According to a first aspect of the present invention, there is provided an integrated circuit for a wireless device according to the present invention, wherein the integrated circuit for a wireless device includes at least a part of a frequency synthesizer circuit and a part of a receiving circuit. The signal generated and output in the receiving circuit as a signal representing the electric field strength is forcibly changed to 0 V when the out-of-synchronization of the frequency synthesizer circuit is detected.
And fixing means for fixing the fixing means.

According to the present invention, the number of signal lines for supplying signals to the control unit can be reduced by one.

According to a second aspect of the present invention, in the integrated circuit for a wireless device according to the first aspect, the fixing means is connected between a signal line of a signal representing a received electric field intensity and a ground, and the frequency synthesizer is provided. The circuit is characterized by comprising a transistor switch controlled by a signal that detects the loss of synchronization of the circuit.

According to a third aspect of the present invention, there is provided a radio telephone apparatus having an integrated circuit including at least a part of a frequency synthesizer circuit and a part of a reception circuit. The integrated circuit is provided with fixing means for forcibly fixing the signal generated in the receiving circuit and output from the integrated circuit to 0 V when the frequency synthesizer circuit is out of synchronization.

According to the third aspect of the present invention, the number of signal lines for supplying signals to the control unit from the integrated circuit including a part of the frequency synthesizer circuit and a part of the receiving circuit can be reduced. It is possible to reduce the restrictions on the board design in the wireless telephone device.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention, wherein 1 is a reference signal oscillator, 2 is a phase comparator, and 3 is L
PF, 4 is a VCO, 5 is a variable frequency divider, and the phase comparator 2 and the variable frequency divider 5 constitute a PLL IC 6. Here, the phase comparator 2 outputs a synchronization detection signal as an output in addition to the phase error signal. The synchronization detection signal becomes H when the frequency synthesizer circuit synchronizes, and becomes L when the frequency synthesizer circuit loses synchronization.

On the other hand, as for reception, the signal received by the antenna 7 is transmitted to the antenna duplexer 8 and the BP for removing spurious signals.
The voltage is applied to the first mixer 12 via the F9, the amplifier 10, and the BPF 11. The first mixer 12 receives the received signal and the PLL IC.
6 to obtain a first intermediate frequency signal (1stIF). The 1st IF is applied to the second mixer 14 after passing through the filter 13, and
It is mixed with the output signal of the second VCO controlled by the IC 6 to obtain a second intermediate frequency signal (2ndIF). After being amplified to a level sufficient for demodulation by the filter 15 and the limiter circuit 16, the second IF operates so as to extract received information by a detection circuit (not shown). The limiter circuit 16 also has a function of detecting a received signal, and generates an RSSI signal here.

Block 2 shown by a dashed line in FIG.
Numeral 0 is a part integrated by IC. That is, FIG.
In the above, the PLL IC 6 forming a part of the frequency synthesizer circuit, the second mixer 14 and the limiter circuit 16 forming a part of the receiving circuit are integrated into one IC.
It is 20.

As shown in FIG. 1, in the output circuit of the RSSI signal, a resistor 17 is inserted in series with a signal line so that an RC circuit for smoothing a fluctuation component can be formed. The capacitor 18 has a limit to what can be realized inside the IC, so that a terminal is provided so that it can be connected from outside the IC.
A transistor switch 19 that is turned on / off by a synchronization detection signal is connected between the signal line of the RSSI signal and the ground.

When the frequency synthesizer circuit is in a synchronous state, the synchronous detection signal is H, so that the transistor switch 19 is opened, and the output of the RSSI signal is not affected. When the synchronization is lost and the synchronization detection signal becomes L, the transistor switch 19 is closed,
The RSSI signal becomes 0V.

FIG. 7 shows the characteristics of the received electric field strength versus the RSSI voltage in the normal operation state in the receiver, where the RSSI voltage is proportional to the received electric field strength, but there is no received electric field. However, a certain amount of detection voltage is generated by noise generated by the receiver itself, and does not become 0 V in any state. Therefore, when the voltage of the RSSI signal is forcibly set to 0 V by the synchronization detection signal,
The control unit can recognize that the frequency synthesizer circuit is out of synchronization.

As described above, according to this embodiment, when the synchronization is lost due to the synchronization detection signal, the RSSI signal is forcibly fixed to 0 V, whereby the synchronization state of the frequency synthesizer circuit can be recognized, and the synchronization state can be recognized. , It can be used as a normal RSSI signal.
The I signal and the synchronization detection signal can be shared.

Here, since the synchronization detection circuit included in the phase comparator 2, the RSSI detection circuit included in the limiter circuit 16, and the transistor switch 19 can be integrated into an IC, the number of circuits can be increased by integrating them into one IC 20. The number of signal lines can be reduced by one without causing any problem.
Therefore, by mounting the IC 20 on a wireless telephone device such as a mobile phone, it is possible to reduce restrictions on the substrate design of the wireless telephone device such as a mobile phone.

In the above description, the case where a part of the frequency synthesizer circuit and a part of the receiving circuit are integrated to form one IC 20 has been described. Even when a part of the synthesizer circuit, a part of the receiving circuit, a part of the transmitting circuit, and the distributor are integrated into one IC 20, the RS
The same operation can be performed by connecting a transistor switch that is ON / OFF controlled by the synchronization detection signal between the signal line of the SI signal and the ground.

[0032]

As described above, according to the integrated circuit for radio equipment of the present invention, the number of signal lines for supplying signals to the control unit can be reduced. In addition, when this integrated circuit is mounted on a wireless telephone device, there is an advantage that restrictions on the substrate design of the wireless telephone device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a frequency synthesizer circuit in a conventional wireless device.

FIG. 3 is a diagram showing a configuration of a phase comparator in the frequency synthesizer circuit.

FIG. 4 is a timing chart showing signals of respective units in the circuit of FIG. 3;

FIG. 5 is a block diagram showing a configuration of a general double superheterodyne receiver.

FIG. 6 is a block diagram showing a configuration of a wireless device in a conventional mobile phone.

FIG. 7 is a diagram showing RSSI voltage characteristics with respect to a received electric field strength in a normal operation state in the receiver.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reference signal oscillator 2 phase comparator 3 low-pass filter (LPF) 4 voltage-controlled oscillator (VCO) 5 variable frequency divider 6 frequency synthesizer IC (PLL IC) 7 antenna 8 common antenna Device 9: Band-pass filter (BPF) 10: Amplifier 11: Band-pass filter (BPF) 12: First mixer 13: Filter 14: Second mixer 15: Filter 16: Limiter circuit 17: Resistor 18: Capacitor 19: Transistor switch 20 ... IC (the part integrated by IC)

Claims (3)

[Claims] An integrated circuit for a radio including at least a part of a frequency synthesizer circuit and a part of a receiving circuit,
A fixing means for forcibly fixing a signal generated and output by the receiving circuit as a signal representing a received electric field strength to 0 V when out of synchronization of the frequency synthesizer circuit is detected. Integrated circuit for radio equipment. 2. The apparatus according to claim 1, wherein said fixing means comprises a transistor switch connected between a signal line of the signal representing the received electric field strength and a ground, and controlled by a signal which detects the loss of synchronization of said frequency synthesizer circuit. The integrated circuit for a wireless device according to claim 1. 3. A wireless telephone device equipped with an integrated circuit including at least a part of a frequency synthesizer circuit and a part of a receiving circuit, wherein the signal is generated in the receiving circuit as a signal representing a received electric field strength and output from the integrated circuit. A fixed signal for forcing a signal to be fixed to 0 V when the out-of-synchronization of the frequency synthesizer circuit is detected.