JPH077454A - Receiver - Google Patents

Abstract

PURPOSE:To shorten the time constant of a loop filter and lockup time required up to phase lock by providing the loop filter with a switch circuit and controlling the switching of the switch circuit at the detection of a receiving state. CONSTITUTION:A detector 7 for detecting a detection output signal from a detector 4 detects the receiving state or non-receiving state of this receiver and its detection signal is supplied to a microcomputer 16. Since a detection signal expressing the receiving state of the detector 7 is not generated when there is no receiving signal for the receiver, the microcomputer 16 detects the non-receiving state and sets up the switch circuit included in the loop filter 15 to OFF so as to shorten the time constant of the filter 15. When the receiving signal is inputted, the microcomputer 16 controls the switch circuit in the filter 15 to ON based upon the detection output signal from the detector 4 and the time constant of the filter 15 is switched so as to be extended and set up so as to obtain a sufficiently large C/N value required for signal reception.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver using a PLL circuit, and more particularly to a receiver suitable for shortening the PLL lockup time during reception of the receiver.

[0002]

2. Description of the Related Art Conventionally, many receivers using a PLL circuit as a local oscillator have been provided in the block diagram shown in FIG. In the figure, 1 is a receiving antenna, 2 is RF
Amplifier and mixer, 3 is an intermediate frequency (IF) amplifier,
The output of the IF amplifier 3 is demodulated into an audio signal by the wave detector 4, amplified by the low frequency amplifier 5 via the switching circuit 9, and output as sound from the speaker 6.

Reference numeral 8 is a squelch circuit, and the squelch circuit 8 controls switching of the AF switching circuit 9 by an output signal from the IF amplifier 3. That is, when the receiving device receives the signal, the switching circuit 9 is turned on by the received signal output of the IF amplifier 3 to supply the audio signal to the low frequency amplifier 5, and when the receiving device does not receive the signal, the switching circuit 9 is turned on.
Turn off to cut off audio signal output.

Reference numeral 10 is a PLL circuit. As is well known, the PLL circuit 10 includes a voltage controlled oscillator 11 (hereinafter referred to as VCO11), a variable frequency divider 12, a phase comparator 13, a reference oscillator 14 and a loop filter 15. The phase-locked loop circuit is formed, and the oscillation output of the VCO 11 is supplied to the RF amplifier and mixer 2. Also, the variable frequency divider 12 is a microcomputer 16
Further, the microcomputer 16 simultaneously controls the time constant switching circuit of the loop filter 15 to set the optimum time constant.

In the receiving device configured as described above, when the key data from the operation key 17 is supplied to the microcomputer 16 at the time of setting the reception frequency, the frequency dividing signal is output from the microcomputer 16 and the frequency dividing signal of the variable frequency divider 12 is output. The frequency ratio is controlled, the phase difference between the output of the variable frequency divider 12 and the reference oscillation signal of the reference oscillator 14 is detected, and the error signal is supplied to the loop filter 15, and at the same time, the loop filter 15 is controlled by the microcomputer 16. A signal was supplied, and the variable frequency divider 11 operated so that the time constant of the time constant switching circuit of the loop filter 15 was set in accordance with the frequency-divided signal every 1 frequency division.

Further, the output error signal from the phase comparator 13 is integrated by the loop filter 15 and converted into a DC voltage corresponding to the error signal, and VCO10 is voltage-controlled by this DC voltage to set the oscillation frequency. .

[0007]

However, in the conventional PLL circuit 10 described above, the frequency division ratio of the variable frequency divider 12 is set by the frequency division signal from the microcomputer 16, and at the same time, the frequency divider 1 of the variable frequency divider 12 is divided. Since the time constant switching circuit of the loop filter 15 is controlled for each time to set the time constant, there is a drawback that the time constant switching signal from the microcomputer 16 is required and the program of the microcomputer 16 becomes complicated.

Further, when the time constant of the time constant switching circuit of the loop filter 15 is set to be long, the time constant switching operation time becomes long and the setting of the oscillation frequency of the VCO 11 cannot be processed in a short time. It was

In particular, when performing intermittent operation in which transmission or reception is repeated in a wireless communication device or the like, in general, when the receiving circuit in the intermittent operation is not operating, a power supply (not shown) is turned off to save power consumption of the receiving device. When the receiver is in the receiving state, the power is automatically turned on. After power on, the above PLL
As described above, the circuit 10 sets the time constant of the loop filter 15 (especially, setting the long time constant when setting the low oscillation frequency).
It takes a lot of time, and the lock-up time until the phase lock of the PLL circuit 10 becomes long has a drawback.

There is also a problem that the longer the intermittent ratio during the intermittent operation, the longer the lock-up time.

The present invention has been made in view of the above points, and an object thereof is to solve the drawbacks of the conventional example and to shorten the PLL lock-up time when setting the oscillation frequency of the PLL circuit 10 to reduce the PLL. The purpose is to provide a receiver that can improve the tracking performance of the VCO11 and increase the time constant of the loop filter after setting the oscillation frequency to obtain the necessary and sufficient C / N for the oscillation frequency of the VCO11.

[0012]

The receiving device of the present invention is
In the receiving device using the VCO of the LL circuit as the local oscillator of the receiving device, a detecting means for detecting the received signal, and
A switching means for switching the time constant of the loop filter of the PLL circuit and a control means for switching control of the switching means by the detecting means are provided, and control is performed so that the time constant of the loop filter becomes short when there is no reception. At the time of reception, the loop filter is controlled so that the time constant becomes long.

Further, the detecting means may be a detecting means for detecting the receiving state from the output signal of the wave detector, and the detecting means may switch the switching means.

Further, in a receiver having a squelch circuit to which the output signal from the IF amplifier is supplied and a switching circuit controlled by the output of the squelch circuit, a switch means for switching the time constant of the loop filter is provided. Alternatively, the output signal of the squelch circuit may be used for switching control.

Further, the switch means for switching the time constant of the loop filter may be controlled to be switched by the output signal of the low frequency amplifier.

Further, a switch means for switching the time constant of the loop filter is connected to a resistor inserted between the phase comparator and the voltage controlled oscillator, and one end of this resistor is grounded by a series circuit of a capacitor and a switch circuit. Alternatively, the switch circuit may be configured to be switched and controlled by a control signal.

[0017]

The receiving device of the present invention uses the PLL circuit as the local oscillator, and when the receiving device is selected, the VCO of the VCO is changed by changing the division ratio of the variable frequency divider of the PLL circuit by the dividing signal from the microcomputer. At the same time as changing the oscillation frequency, the time constant of the loop filter is switched according to the oscillation frequency, and an oscillation frequency signal with good C / N is sent from the VCO to the RF amplifier and mixer for high quality reception.

Detecting means for detecting the reception state by the detector by the detection output signal from the detector of the receiving device, or detecting means for detecting the output signal from the IF amplifier by the squelch circuit,
Alternatively, detection means for detecting the audio output signal via the rectifying circuit and the integrating circuit is provided, and the detection signal detected by this detection means is supplied to the microcomputer.

According to the detection signal, the microcomputer described above
The switching circuit provided in the loop filter of the PLL circuit for switching the time constant is switched and controlled. This loop filter comprises a resistor inserted between a phase comparator and a voltage controlled oscillator, and a low-pass filter configured such that one end of this resistor is grounded by a series circuit of a capacitor and a switch circuit.

When the above switch circuit is turned off, the electric charge charged in the capacitor is retained and the switch circuit
When turned on, the electric charge charged in the capacitor is discharged.

That is, when the receiving device does not receive data, the switch circuit is turned off, the capacitor of the loop filter is not grounded, and the time constant is controlled to be short, so that the lockup time of the PLL circuit can be shortened. On the other hand, when a signal is received, the switch circuit is turned on and the capacitor is grounded so that the time constant becomes a predetermined time constant and is controlled to be long, and the C / N of the VCO oscillation frequency signal of the PLL circuit is in a good state. be able to.

As described above, when the receiving device performs the intermittent operation, the time constant of the loop filter is switched and controlled in synchronization with the intermittent operation, so that the lockup time of the PLL circuit can be shortened even if the intermittent ratio becomes long. It is possible to

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a receiver according to the present invention will be described with reference to FIGS. The same parts as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted. 1 is a block diagram showing a first embodiment, FIGS. 2 and 3 are block diagrams showing other second and third embodiments, and FIGS. 4 and 5 are time constant changeover switch circuits of loop filters. It is the circuit diagram which showed.

In FIG. 1 (first embodiment), 7 is a detector for detecting the detection output signal of the detector 4. The detector 7 can detect the receiving state or non-receiving state of the receiving device. Then, this detection signal is supplied to the microcomputer 16. As shown in FIG. 4, the loop filter 15 of the PLL circuit 10 forms a low-pass filter circuit including a resistor R and a capacitor C, and is grounded from the capacitor C via the switch circuit 20.

When setting the reception frequency of the receiver, the operation key 17
When the key data from is supplied to the microcomputer 16, the microcomputer 16 sends a frequency-divided signal based on the key data to the variable frequency divider 12 to change the division ratio and change the oscillation frequency of the VCO11 to receive the signal from the receiving device. Operates to set the frequency. At the same time, the microcomputer 16 sends a time constant switching control signal for the loop filter 15 to set the time constant of a time constant switching circuit (not shown).

Now, when there is no received signal from the receiving device, the detection signal representing the receiving state of the detector 7 is not generated, so the microcomputer 16 detects this non-reception state and the loop filter 15 is detected. The switch circuit 20 provided is set to OFF so that the loop filter 15 has a short time constant. That is, the PLL circuit 10 can operate in a short lock-up time and be phase-locked without discharging the electric charge charged in the capacitor C.

When the received signal is detected, the microcomputer 16 controls the switch circuit 20 of the loop filter 15 to be ON by the detection output signal from the wave detector 4, and the time constant of the loop filter 15 is switched to be long, so that the signal is received. Can be set so that a necessary and sufficient C / N can be obtained.

When the receiving device is, for example, a wireless communication device,
Loop filter when the power of the wireless communication device is turned on
The switch circuit 20 of 15 is set to ON. However, when the wireless communication device performs the intermittent operation in the reception state and the transmission (non-reception) state, when the intermittent operation is not received, that is, when the power is turned off to save power, the switch circuit 20 of the loop filter 15 is turned on.
Is set to OFF.

That is, similarly to the above, the capacitor C of the low-pass filter is not grounded, and the electric charge charged in the capacitor C is retained as it is, so that the lockup time during the oscillation frequency setting operation of the PLL circuit 10 can be shortened. .

In particular, even if the time constant of the loop filter 15 is set to a long time constant, the lock-up time can be kept short and the radio communication device can maintain a high-speed reception state.

On the other hand, when the wireless communication device catches the received radio wave and enters the receiving state, the power of the receiving circuit is turned on, the intermittent operation is set to the receiving on state, and the switch circuit 20 of the loop filter 15 is turned on. Then, the electric charge held in the capacitor C is discharged, and the time constant corresponding to the original oscillation frequency of the VCO 11 can be set.

As described above, the charge control of the capacitor C can be controlled by the switching control of the switch circuit 20 connected in series with the capacitor C, and the followability of the phase lock of the PLL circuit 10 can be improved. Since the intermittent ratio can be increased, the power consumption of the wireless communication device can be reduced.

FIG. 2 (second embodiment) shows a squelch circuit 8 to which an output signal of the IF amplifier 3 is supplied, and an AF (audio frequency) of an audio signal for controlling an audio output by the squelch signal from the squelch circuit 8. Switching circuit 9
It is an example of a receiving device having.

The receiving state of this receiving device is the squelch circuit 8
The AF switching circuit 9 is turned off by the squelch signal when the receiving device is not receiving, so that the audio output from the speaker 6 is not output.
Block input to. On the other hand, the squelch output signal of the squelch circuit 8 is supplied to the loop filter 15 of the PLL circuit 10, and the switch circuit 20 of the loop filter 15 shown in FIG.
By controlling to OFF, the lockup time of the PLL circuit 10 can be shortened as described above.

When the receiving device receives the received signal,
The AF switching circuit 9 is turned on by the squelch signal of the squelch circuit 8, and the audio signal can be output from the speaker 6. At the same time, the switch circuit 20 of the loop filter 15 is turned on by the squelch signal, and the time constant switching circuit is turned on. It is possible to lengthen the time constant of, and to improve the C / N of the oscillation frequency signal of the PLL circuit 10 with respect to the received signal to perform high quality reception.

FIG. 3 (third embodiment) shows a rectifier circuit 18 to which the output signal from the low frequency amplifier 5 is supplied, and this rectifier circuit 18.
An integrator circuit 19 to which the rectified output of 18 is supplied is provided, and an integrated output signal of the integrator circuit 19 is supplied to the loop filter 15 to switch and control the switch circuit 20 of the loop filter 15 shown in FIG. It is a thing.

When there is no output audio signal from the low-frequency amplifier 5, the receiving device is in a non-reception state, the squelch signal from the squelch circuit 8 sets the AF switching circuit 9 to OFF, and the audio output is This is the case when it is blocked. In this case, the DC output voltage of the integrating circuit 19 is not generated, and the switch circuit 20 of the loop filter 15
Is set to OFF, the capacitor C of the low-pass filter is not grounded, and the charge charged in the capacitor C is retained as it is.

That is, as described above, the lock-up time of the PLL circuit 10 is shortened and the followability of the phase lock operation can be improved.

When the receiving device is in the receiving state, that is, when the AF switching circuit 9 from the squelch circuit 8 is in the ON state and the audio output signal is supplied to the low frequency amplifier 5, the low frequency amplifier 5 The output signal of the rectifier circuit 18
Is converted into a DC output voltage by the integration circuit 19 and the switch circuit 20 of the loop filter 15 is controlled to be ON. That is, the time constant of the loop filter 15 is set to a necessary and sufficient time constant, and the oscillation frequency of the VCO 11 having a good C / N can be obtained.

As described above, the loop filter 15 of the PLL circuit 10 is
Although the low-pass filter circuit formed by the resistor R and the capacitor C shown in FIG. 4 has been described, as shown in FIG. 5, the first capacitor C1 having a relatively small capacity is grounded and is connected in series with the second capacitor C2. A low-pass filter circuit configured to be grounded via the connected switch circuit 20 may be used, and the switch circuit 20 may be formed of a semiconductor switch such as a transistor, and any of them can achieve the same effect as described above. it can.

Further, the time constant switching circuit of the loop filter 15 is composed of a plurality of capacitors and a plurality of switch circuits connected in series with the plurality of capacitors, and the plurality of switch circuits are subjected to predetermined switching control by the control signal described above. Can also be configured to do.

[0042]

As described above, the receiver according to the present invention is provided with the switch circuit in the loop filter of the PLL circuit,
Since this switch circuit is configured to perform switching control by detecting the reception state, when the receiving device is not receiving or when the intermittent operation is OFF, the switch circuit is controlled to OFF to shorten the time constant of the loop filter and phase lock of the PLL circuit. This has the effect of shortening the lock-up time until it becomes possible to enable high-speed channel selection.

When the received signal is detected, the switch circuit is turned on and the time constant is lengthened, so that the C / N of the oscillation frequency signal of the VCO can be improved. In particular, since it is only necessary to switch the above switch circuit to ON after receiving the received signal, the VCO oscillates at a comparatively low oscillation frequency and the loop filter can be operated at any intermittent ratio during intermittent operation. Even when the time constant is set to a long value, the lockup time for the PLL circuit to phase lock can be shortened, and a high-quality VCO oscillation frequency signal can be obtained.

Further, unlike the conventional example, the time constant switching control of the loop filter does not need the microcomputer control for switching the time constant every 1 frequency division of the variable frequency divider, and the microcomputer program can be simplified. Since the lockup time can be shortened, there is an effect that the operation time at the time of intermittent operation can be shortened, the power consumption of the power source can be reduced, and the power consumption can be reduced.

Moreover, it has excellent features such as a simple structure and easy implementation because it can be constructed at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a receiving apparatus according to the present invention.

FIG. 2 is a block diagram showing another second embodiment using a squelch circuit.

FIG. 3 is a block diagram showing another third embodiment in which a control signal is generated from an audio output.

FIG. 4 is a circuit diagram showing a loop filter.

FIG. 5 is a circuit diagram showing another loop filter.

FIG. 6 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 reception antenna 2 RF amplifier and mixer 3 IF amplifier 4 detector 5 low frequency amplifier 6 speaker 7 detector signal detector 8 squelch circuit 9 AF switching circuit 10 PLL circuit 11 voltage controlled oscillator (VCO) 12 variable frequency divider 13 phase Comparator 14 Reference oscillator 15 Loop filter 16 Microcomputer 17 Operation key 18 Rectifier circuit 19 Integrator circuit 20 Switch circuit

Claims (5)

[Claims] 1. A receiving device using a voltage controlled oscillator of a phase locked loop (PLL) circuit as a local oscillator of the receiving device, a detecting means for detecting a received signal, and a switch for switching a time constant of a loop filter of the PLL circuit. Means and control means for switching control of the switch means by the detection means are provided so that the time constant of the loop filter becomes short when there is no reception, and the time constant of the loop filter becomes long when a signal is received. A receiving device characterized by being controlled so that. 2. The receiving means according to claim 1, wherein said detecting means is a detecting means for detecting a receiving state from an output signal of the wave detector, and said detecting means controls switching of said switch means. apparatus. 3. A receiver having a squelch circuit to which an output signal from an intermediate frequency (IF) amplifier is supplied and a switching circuit controlled by the output of the squelch circuit, wherein the time constant of the loop filter is switched. 2. The receiving device according to claim 1, wherein the switch means is switch-controlled by an output signal of the squelch circuit. 4. The receiving apparatus according to claim 1, wherein the switching means for switching the time constant of the loop filter is switching-controlled by the output signal of the low frequency amplifier. 5. A switch means for switching the time constant of the loop filter, wherein a resistor inserted between the phase comparator and the voltage controlled oscillator and one end of this resistor are grounded by a series circuit of a capacitor and a switch circuit. 4. The receiving device according to claim 1, wherein the receiving circuit is configured to be switched and controlled by a control signal.