JP2003209469A - Oscillator, phase-locked loop circuit, and tuning device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a VCO into low phase noise over a wide frequency band in a television system utilizing a phase-locked loop circuit. <P>SOLUTION: A tuner IC70 inputs a signal V3 obtained by mixing a received wave f5 and an oscillated signal f3 of a VCO 20 in a mixer part 72 to a digital signal demodulation IC 82. The digital signal demodulation IC 82 demodulates video or audio by digital signal processing, detects a bit error rate BER during digital signal processing and inputs it to a CPU84. The CPU84 produces data VD corresponding to a current control signal for making the BER into prescribed level and inputs the data to a data converter 76. The data converter 76 converts the data VD to an analog current control signal and inputs it to a current control terminal 25 of the VCO 20. A variable current source 29a switches and controls the operating current of an oscillation circuit 26 on the basis of the current control signal. By switching and controlling the operating current of the oscillation circuit 26, the phase noise of the oscillation circuit 26 is maintained at the prescribed level. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in an oscillator, a phase locked loop (PLL) circuit using the oscillator, or a receiving or transmitting device such as a television device or a mobile phone. The present invention relates to a tuning device such as a PLL frequency synthesizer or tuner using a phase synchronization circuit. In particular, it relates to improvement of phase noise characteristics.

[0002]

2. Description of the Related Art In various communication devices (transmitters and receivers), tuning devices (tuning circuits) such as frequency synthesizers and tuners are used for frequency conversion of transmission signals and reception signals. And, for these, for example, a voltage controlled oscillator is used to configure a local oscillation circuit or the like. Further, a phase locked loop circuit using this voltage controlled oscillator may be incorporated.

FIG. 6A is a block diagram showing the basic structure of a phase locked loop circuit. This phase synchronization circuit 1 is
An L integrated circuit (PLLIC) 10 and a VCO (Voltage Cont) having a frequency control input terminal 22 and an output terminal 24.
A roled oscillator) 20 and a loop filter circuit 30 are provided. The PLLIC 10 has a reference oscillator 12 that generates a voltage signal f1 having a reference frequency, variable frequency dividers 14 and 16 such as programmable counters, and a phase comparator 18, which are integrated into a single chip. .

The VCO 20 generates a voltage signal f3 having a frequency corresponding to the control signal input to the frequency control input terminal 22, and outputs it from the output terminal 24. Variable frequency divider 14
Is the voltage signal f1 output from the reference oscillator 12
The frequency is divided into A and the divided output signal f2 is input to one terminal 18a of the phase comparator 18. The variable frequency divider 16 is VC
The voltage signal f3 output from O20 is divided into 1 / N,
The divided output signal f4 is sent to the other terminal 1 of the phase comparator 18.
Enter in 8b. Dividing ratio of variable dividers 14 and 16 1 /
A and 1 / N are designated by, for example, a microcomputer (not shown). The phase comparator 18 compares the phases of the two voltage signals f3 and f4, and inputs an error signal indicating the phase difference, which is the comparison result, to the loop filter circuit 30. The loop filter circuit 30 has two voltage signals f3 and
The phase comparison result (error signal) of f4 is smoothed, and this smoothed signal is applied to the frequency control input terminal 22 of the VCO 20 as a frequency control signal.

In the phase locked loop circuit 1, the output voltage signal f3 from the VCO 20 is divided by the variable frequency divider 16 in the PLLIC 10 at a division ratio of 1 / N, and the PLLIC 10 is then divided.
The output signal f4 of the variable frequency divider 16 and the signal f2 obtained by dividing the output signal f1 of the reference oscillator 12 into 1 / A are phase-compared by the internal phase comparator 18, and the output voltage V0 of the phase comparator 18 is obtained. Is converted into a frequency control signal V1 through the loop filter circuit 30 and supplied to the VCO 20,
The oscillation frequency of 0 is controlled.

FIG. 6B shows V in the phase locked loop circuit 1.
It is a circuit diagram showing a conventional example of CO20. VC shown
O20 is an oscillation circuit (resonance circuit) 26 and a frequency control circuit 27 having NPN transistors Q21 to Q24.
And NPN type transistors Q25 and Q26, a resistance element R
21, R22, and a current source unit 28 having a reference voltage source VT21.

The transistors Q21 and Q22 and the transistors Q23 and Q24 which form the frequency control circuit 27 are cascade-connected. Transistor Q2
1, Q23 are base commons, and their respective collector terminals are connected. The base terminal and the collector terminal are connected to a predetermined portion in the VCO 20. The transistors Q22 and Q24 have their emitter terminals connected to the corresponding input terminals a and b of the oscillator circuit 26, their respective base terminals connected to the corresponding input terminals c and d of the oscillator circuit 26, and have a frequency between both ends. A control signal is applied. That is, in this example, the transistors Q22 and Q2 are
The base terminal of 4 functions as a frequency control input terminal. For example, the reference potential is applied to one of the base terminals of the transistors Q22 and Q24, and the frequency control signal V1 (voltage signal) from the loop filter circuit 30 is applied to the other terminal.

Transistor Q2 constituting current source unit 28
The reference voltage source VT21 is connected to the base terminals of the terminals Q5 and Q26. Further, a resistor element R for setting current is provided between each emitter terminal and the ground.
21 and R22 are connected, and each collector terminal is
Transistors Q22 and Q that form the frequency control circuit 27
It is connected to 24 corresponding emitter terminals.

Transistor Q25 and resistance element R2
1, the transistor Q26 and the resistance element R22 form a current setting circuit (constant current source).
The collector currents I25 and I26 of 25 and Q26 are the output voltage value of the reference voltage source VT21 and the resistance elements R21 and R22.
And is almost constant. Also, the transistor Q22
The sum current I01 of the emitter current of the transistor Q25 and the current from the terminal a of the oscillation circuit 26 is the collector current I2 of the transistor Q25.
5, the sum current I02 of the emitter current of the transistor Q24 and the current from the terminal b of the oscillation circuit 26 is equal to the collector current I26 of the transistor Q26, and the sum currents I01 and I02 are constant. That is, the oscillator circuit 26
Is driven by a constant current determined by the reference voltage source VT21 and the resistance elements R21 and R22.

[0010]

A VC having such a configuration
O20 generates a voltage signal having a frequency corresponding to the control signal applied between the base terminals of the transistors Q22 and Q24. That is, by controlling the magnitude of the frequency control signal, the oscillation frequency can be controlled over a wide band. However, although the VCO 20 having the above-described configuration can control the oscillation frequency over a wide band, it has been impossible to achieve low phase noise over a wide band even if the phase noise is low at a certain oscillation frequency.

The increase in phase noise is caused by the performance of a tuning device such as a PLL frequency synthesizer or tuner using a phase synchronization circuit, or a receiving or transmitting device such as a television device or a mobile phone using this tuning device. It becomes a factor to reduce the noise, and it is inconvenient in constructing a high-performance phase locked loop. For example, since the phase noise is the most important characteristic among the characteristics of the digital TV considered as the application of the phase locked loop, the deterioration of the phase noise should not occur.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an oscillator capable of controlling its oscillation frequency over a wide band without causing an increase in phase noise. Another object of the present invention is to provide a phase synchronization circuit that does not have a problem of phase noise over a wide frequency band, or a tuning device used in a transmitter, a receiver or the like.

[0013]

According to a study by the inventors of the present application, it has been found that the phase noise fluctuates when the drive current (operating current) flowing in the oscillation circuit constituting the voltage controlled oscillator is changed. . The present invention is based on such knowledge. That is, the oscillator according to the present invention has a configuration in which the operating current of the oscillator can be controlled according to the oscillation frequency. Specifically, the oscillator according to the present invention includes an oscillation circuit that oscillates at a predetermined frequency, a frequency control circuit that controls the oscillation frequency of the oscillation circuit based on the input frequency control signal, and an input current control signal. And an operating current control circuit for controlling the operating current of the oscillation circuit based on the above.

Further, the phase locked loop circuit and the tuning device according to the present invention include an oscillator having a structure capable of controlling such an operating current according to the oscillation frequency. Further, in this phase synchronization circuit or tuning device, in order to make the operating current controllable in accordance with the oscillation frequency, for example, a current control signal is generated based on the frequency of the output signal output from the oscillator. A current control unit for applying the generated current control signal to the current control input terminal may be provided. Alternatively, a phase noise monitoring unit that detects the phase noise of the output signal output from the oscillator, generates a current control signal based on the detected phase noise, and applies the generated current control signal to the current control input terminal is provided. You may prepare.

[0015]

In the oscillator having the above structure, the operating current control circuit controls the operating current of the oscillation circuit based on the current control signal, whereby the phase noise at each oscillation frequency can be adjusted. This control operation may be manually set by the user. Alternatively, if a current control unit is provided, a current control signal according to the oscillation frequency can be automatically calculated. Furthermore, if a phase noise monitoring unit is provided, it is possible to automatically detect the phase noise of the oscillator output and perform feedback control based on the result.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of an oscillator according to the present invention. The basic structure is the same as that of the prior art except for the current source section 28. Therefore, the same reference numerals as those shown in FIG.
The explanation of the function is omitted. The illustrated VCO 20 is provided with a component for switching the operating current of the oscillation circuit 26 in the current source section 28 thereof, and there are two switching states (A) in FIG. 1 (A) and FIG. 1 (B). Is switch SW1
Is off and B is on).

More specifically, the VCO 20 has a current setting circuit (constant current source) formed by a transistor Q25 and a resistance element R21, and a current setting circuit formed by a transistor Q31 and a resistance element R31. Similarly, a transistor Q32 and a resistance element R22 are provided together with a current setting circuit including a transistor Q26 and a resistance element R22.
It has a current setting circuit consisting of 32. Transistor Q3
The base terminals of 1, Q32 are transistors Q25, Q2.
Like the base terminal of No. 6, it is connected to the reference voltage source VT21. The collector terminal of the transistor Q31 is connected to the collector terminal of the transistor Q25, and the collector terminal of the transistor Q32 is connected to the collector terminal of the transistor Q26.

On the left side of each drawing, a constant current source having a current mirror structure having a resistance element R33 and three transistors Q33, Q34, Q35 is provided. The switch SW1 is provided between the base terminal of the transistor Q33 and the internal connection line e, and the switches SW1 and Q3 are connected to each other.
The collector terminal of 5 is connected to the internal connection line e. The emitter terminal of the transistor Q35 is commonly connected to the emitter terminals of Q31 and Q32. That is, the resistance element R33 and the three transistors Q33, Q34, Q
A current switching circuit 29 is configured by 35 and the switch SW1. The current source unit 28 including the current switching circuit 29 constitutes the operating current control circuit according to the present invention. The control terminal CNT of SW1 functions as a current control input terminal.

First, as shown in FIG. 1A, the switch S
When W1 is off, the current switching circuit 29 is off (state in which the constant current does not operate), and the collector current I35 of the transistor Q35 is "0;zero". For this reason,
Each of the current setting circuits of the transistor Q31 and the resistance element R31 and the transistor Q32 and the resistance element R32 provided in the conventional current source unit 28 is turned on, and the transistor Q31
A collector current I31 flows through 31, and a collector current I32 flows through the transistor Q32. For this reason,
The sum current I01 of the emitter current of the transistor Q22 that constitutes the frequency control circuit 27 and the current from the terminal a of the oscillator circuit 26 is equal to the sum of the collector current I25 of the transistor Q25 and the collector current I31 of the transistor Q31 (I01 = I25 + I31 ), And transistor Q2
4 of the emitter current and the current from the terminal b of the oscillation circuit 26, the sum current I02 is the collector current I of the transistor Q26.
26 and the collector current I31 of the transistor Q31 are equal (I02 = I26 + I32).

On the other hand, as shown in FIG. 1 (B), when the switch SW1 is on, the current switching circuit 29 is on (state of constant current operation). Transistor Q at this time
The collector current I35 of 35 is twice as large as I0 (I0 = 2 *
I0). This current I35 is applied to the transistor Q35.
Flows through the emitter terminals of the resistor elements R31 and R32. Assuming that the resistance values of the resistance elements R31 and R32 are equal, a current I0 is applied to each of the resistance elements R31 and R32.
Flows. As a result, a voltage is generated across the resistance elements R31 and R32, and the voltage Ve at the emitter terminals of the transistors Q31 and Q32 rises. At this time, the voltage Ve at the emitter terminal is the voltage value Vb-Vb of the reference voltage source VT21.
If the collector current I35 of the transistor Q35 is set to a value larger than e (Vbe is a base-emitter voltage), the base-emitter of the transistors Q31 and Q32 is reversely biased and is completely turned off. Therefore, the sum current I01 of the emitter current of the transistor Q22 that constitutes the frequency control circuit 27 and the current from the terminal a of the oscillation circuit 26 is equal to the collector current I25 of the transistor Q25 (I01 = I25), and the emitter of the transistor Q24 is The sum current I02 of the current and the current from the terminal b of the oscillation circuit 26 becomes equal to the collector current I26 of the transistor Q26 (I02 = I26). That is, the state becomes the same as that of the conventional VCO 20.

As described above, according to the VCO 20 of the above-described embodiment, the sum currents I01 and I02, that is, the operating current of the oscillation circuit 26 can be switch-controlled by switching the switch SW1 on / off. As described above, according to the investigation by the inventors of the present application, when the operating current flowing through the oscillation circuit 26 forming the VCO 20 is changed, the phase noise changes. Therefore, in the VCO 20 having the above configuration, 2
Although there is a stage, by switching the switch SW1 according to the oscillation frequency of the oscillation circuit 26, it is possible to reduce the phase noise over a wide frequency band by switching to a more appropriate operating current according to the oscillation frequency. it can.

In the configuration of the above embodiment, the operating current value is switched in two steps by one switch SW1. However, for example, a plurality of circuits similar to the current switching circuit 29 are connected to change the current. If you switch,
The operating current can be switched at another stage. Further, when the collector current I35 of the transistor Q35 is small, the transistors Q31 and Q32 are not completely turned off, and become an active state (active state) corresponding to the current state, and a certain amount of collector current flows. Therefore, in this case, according to the collector current amount, the sum current I01,
I02 is replaced with I25 to I25 + I31 or I25, respectively.
It can be controlled within the range of 26 to I26 + I32. Further, for example, if the resistance element R33 is replaced with a variable resistance or FET and the resistance value (ON resistance value in the case of FET) of the switch SW1 can be changed and controlled, the sum currents I01 and I02 are respectively changed. I25 ~
It can be dynamically changed within the range of I25 + I31 or I26 to I26 + I32. In other words, by varying the value of the variable resistor so that the operating current of the oscillation circuit 26 has an appropriate current value according to the oscillation frequency, it is possible to dynamically reduce the phase noise. The same applies when the current switching circuit 29 is replaced with a variable current source capable of changing the output current corresponding to the current value I35. Also, by monitoring the phase noise, the transistor Q35
With a feedback configuration in which the collector current I35 of (1) is dynamically changed according to the phase noise, the configuration automatically follows the optimum operating current value, and low phase noise is always obtained.

FIG. 2 is a block diagram showing an embodiment of a phase locked loop having the VCO 20 shown in FIG. Since the influence of the phase noise appears as the jitter (frequency fluctuation) of the oscillation output f3 of the VCO 20, the phase synchronization circuit 1 adopts the method of detecting the phase noise by detecting the jitter amount of the output signal f3 of the VCO 20, Oscillation circuit 26
The feedback configuration is such that the operating current is switched based on the amount of jitter. That is, the phase synchronization circuit 1
Includes a jitter amount monitoring circuit 90 which is an example of a phase noise monitoring unit that monitors the oscillation output f3 of the VCO 20, that is, the jitter amount of the output frequency of the oscillation circuit 26. In FIG. 2, V
The CO20 is shown in a block diagram, but this VCO20
1 has the configuration shown in FIG.

A predetermined threshold value is input to the jitter amount monitoring circuit 90. This threshold is set by a CPU (not shown) or the like. Then, the jitter amount monitoring circuit 90 compares the monitored jitter amount of f3 with the threshold value, and outputs a current control signal for turning on / off the switch SW1 (see FIG. 1) of the current switching circuit 29 according to the magnitude. Input to the current control input terminal 25. It is preferable that the jitter amount monitoring circuit 90 has a Schmitt configuration so that hunting does not occur when the switch SW1 is switched.

The oscillating circuit 26 is assumed to have such a characteristic that the phase noise increases when the oscillation frequency is high and the phase noise decreases when the operating current amount is large (hereinafter, also referred to as monotonous decrease characteristic). In this case, the jitter amount monitoring circuit 90 turns off the switch SW1 shown in FIG. 1 when the oscillation frequency of the oscillation circuit 26 becomes high and the monitored jitter amount of f3 becomes larger than the threshold value.
The operating current of the oscillator circuit 26 is increased. This gives f3
The phase noise of will be reduced.

On the other hand, when the oscillation frequency of the oscillation circuit 26 becomes low and the monitored jitter amount of f3 becomes smaller than the threshold value, the jitter amount monitoring circuit 90 turns on the switch SW1 shown in FIG. The operating current of the circuit 26 is reduced. As a result, the phase noise of f3 returns to the original amount. In this case, since the oscillation frequency of the oscillation circuit 26 is low, the jitter amount of f3 does not matter. That is, although there are two stages, the phase noise of the oscillation circuit 26 is monitored based on the jitter amount of f3, and the oscillation circuit 2
By switching the operating current of No. 6, it is possible to perform feedback control so that the phase noise is always a predetermined amount or less.

As described above, in the configuration shown in FIG. 2, since the operating current of the oscillation circuit 26 can be changed by switching the switch SW1, the operating current of the oscillation circuit 26 is prevented so that the phase noise does not become a problem. Can be optimized, and as a result, low phase noise can be obtained over a wider voltage controlled oscillation frequency band than the conventional configuration in which the operating current is fixed. When the phase noise characteristic with respect to the oscillation frequency of the oscillation circuit 26 has a characteristic opposite to the above (hereinafter also referred to as a monotonically increasing characteristic), the jitter amount monitoring circuit 90 switches the operating current of the oscillation circuit 26 with the characteristic reverse to the above. Good.

FIG. 3 is a diagram showing a modification of the phase locked loop circuit 1 shown in FIG. First, the current source unit 28 has a variable current source 29a capable of changing the output current according to the control voltage, instead of the current switching circuit 29. In addition, the phase synchronization circuit 1
Instead of the jitter amount monitoring circuit 90 for turning on / off the switch SW1 of the current switching circuit 29, a jitter amount monitoring circuit for inputting a control voltage Vc corresponding to the jitter amount of f3 to the current control input terminal 25 as a current control signal. It has 92. The variable current source 29a has such a characteristic that the output current increases when the control voltage Vc is high, for example.

In this case, as described above, when the oscillation circuit 26 has the monotonous decreasing characteristic that the phase noise increases when the oscillation frequency is high and the phase noise decreases when the operating current amount is large, the jitter is reduced. The quantity monitoring circuit 92 makes the control voltage Vc higher when the oscillation frequency of the oscillation circuit 26 increases and the monitored jitter amount of f3 increases. Thereby, the variable current source 29a
The amount of current flowing through the oscillator increases, the operating current of the oscillator circuit 26 increases, and the phase noise of f3 decreases.

On the other hand, when the oscillating frequency of the oscillating circuit 26 decreases and the monitored jitter amount of f3 decreases, the jitter amount monitoring circuit 92 makes the control voltage Vc lower. As a result, the amount of current flowing through the variable current source 29a decreases, the operating current of the oscillation circuit 26 decreases, and the phase noise of f3 increases. That is, in the configuration shown in FIG. 3, the phase noise of f3 is monitored based on the jitter amount of f3 and the operating current of the oscillation circuit 26 is continuously controlled (switched), so that the phase noise is always a predetermined amount. Feedback control can be performed dynamically.

As described above, in the configuration shown in FIG.
Since the operating current of the oscillating circuit 26 is dynamically changeable, the operating current of the oscillating circuit 26 can be optimized for each oscillation frequency. Phase noise can be obtained.

When the phase noise characteristic with respect to the oscillation frequency of the oscillation circuit 26 is the monotonically increasing characteristic opposite to the above,
The jitter amount monitoring circuit 92 may control the operating current of the oscillation circuit 26 with the characteristics reverse to those described above. When the characteristic is not monotonically increasing or monotonically decreasing, the control voltage Vc is sequentially varied to search and set the Vc value that minimizes the detected jitter amount, and the optimum current amount that minimizes the phase noise is set. It is better to set it.

FIG. 4 is a diagram showing another modification of the phase locked loop circuit 1. In the embodiments shown in FIGS. 2 and 3, the jitter amount of the signal f3 output from the oscillation circuit 26 is detected, and the operating current of the oscillation circuit 26 is controlled based on the detection result. In the embodiment shown in FIG. 4, the oscillation circuit 26 is based on the oscillation frequency of the oscillation circuit 26.
The operating current of is controlled. Therefore, first, the current source unit 28 has a variable current source 29a capable of changing the output current according to the control voltage Vc, as in the case shown in FIG. Further, instead of the jitter amount monitoring circuit 92 shown in FIG. 3, a CPU 84 for controlling the entire apparatus using the phase locked loop 1 is provided. The CPU 84 is the variable frequency divider 1
PLLIC of tuning control data for switching the division ratios 1 / A and 1 / N of 4 and 16 (either one may be sufficient)
Enter in 10. It also has a function of the current control unit according to the present invention, which applies the control voltage Vc according to the set frequency division ratio to the current control terminal 25.

As described above, when the operating current of the oscillation circuit 26 is constant, its phase noise differs depending on the oscillation frequency. In other words, if the correspondence relationship between the oscillation frequency, the phase noise, and the operating current is acquired in advance, the phase noise can be set to a predetermined level by controlling the operating current according to the oscillation frequency. This embodiment utilizes this.

For example, as described above, the oscillation circuit 26
It is assumed that the phase noise increases when the oscillation frequency is high, and the phase noise decreases when the operating current amount is large. The oscillation frequency of the oscillation circuit 26 is the CPU 8
It is determined by setting the frequency division ratios in the variable frequency dividers 14 and 16 according to No. 4. Therefore, when the frequency division ratio is set so that the oscillation frequency of the oscillation circuit 26 becomes high, the CPU 84 makes the control voltage Vc to the current control terminal 25 higher in accordance with this. Thereby, the variable current source 29a
The amount of current flowing through the oscillator increases, the operating current of the oscillator circuit 26 increases, and the phase noise of f3 decreases.

On the other hand, when the frequency division ratio is set so that the oscillation frequency of the oscillation circuit 26 becomes low, the CPU 84 makes the control voltage Vc to the current control terminal 25 lower accordingly. As a result, the amount of current flowing through the variable current source 29a decreases, the operating current of the oscillation circuit 26 decreases, and the phase noise of f3 increases. However, since the oscillation frequency of the oscillation circuit 26 is low, the level of potential phase noise is low.

That is, in the configuration shown in FIG. 4, the operating current of the oscillation circuit 26 is controlled (switched) based on the oscillation frequency of the oscillation circuit 26, so that the configuration is not the feedback configuration (the open loop configuration). , The phase noise can be controlled so as to be a predetermined amount.

For the control voltage Vc corresponding to the frequency, the data acquired in advance is used as a lookup table (LU
It is preferable that the data is stored in the memory after being set to T) and that data is used. Further, in the above description, the CPU 84 that manages the oscillation frequency uses the variable frequency divider 1 set by itself.
Although the control voltage Vc is generated according to the division ratio of 4 and 16, for example, the oscillation frequency of the oscillation circuit 26 may be detected and the control voltage Vc may be generated according to the detected frequency. .

FIG. 5 is a block diagram showing an example of a television system (television receiving system) including a tuner having the VCO 20 of the above embodiment. This television system 3 has a bit error rate (BER;
(Bit Error Rate) is detected and the VCO 20 is fed back to automatically set the operating current of the VCO (in particular, the oscillation circuit portion) to an optimum current value. That is, the illustrated television system 3 has a tuner I
C70, a high-frequency signal receiving circuit 80 that is an example of a receiving unit that receives a television signal that is an example of a communication signal, and MPEG- based on a signal that is output from the tuner IC 70.
A digital signal demodulation IC 82 for demodulating the TS signal and a CPU 84 for controlling the entire television system 3 are provided.

The tuner IC 70 includes a VCO 20 and a loop filter circuit 30, and mixes the phase locked loop circuit 1 functioning as a local oscillator circuit, the received wave f5 input from the high frequency signal receiving circuit 80 and the output signal f3 of the VCO 20. And a mixer section (mixing circuit) 72 that mixes and extracts an intermediate frequency (IF) signal of 57 MHz (meaning that the center of the IF signal is 57 MHz) V3, and the IF signal V3 output from the mixer section 72 is amplified to a predetermined level. IF
It has an amplifier 74 and a data converter 76, which are integrated into a single chip. In the case of a system that receives a television signal wirelessly, the high-frequency signal receiving circuit 80 transmits a television signal via an antenna or, in the case of a system that receives a cable such as CATV (cable television), via a cable. Entered in.

The phase synchronization circuit 1 has the configuration shown in FIG. Oscillation circuit 2 that constitutes the VCO 20
6 includes, for example, VHF band (1 to 12CH; 90 to
222MHz) and UHF band (13 to 62CH; 470 to 470)
It is also possible to provide a resonance circuit that oscillates at a frequency according to the tuning frequency band such as 770 MHz) and switch these.

Here, when the received wave (received channel image carrier) f5 and the output f3 of the oscillation circuit 26 functioning as a local oscillation circuit are mixed in a circuit having a nonlinear input / output relationship, the signal of f5 + f3 and f5- The signal of f3 is generated.
In the television system 3, the frequency f3 of the oscillator circuit 26 (that is, the local oscillator circuit) is 57 MHz from the received wave f5.
The frequency is increased by z, and the mixer 72 is provided with a 57 MHz resonance circuit to extract a signal of f5-f3 = 57 MHz as an intermediate frequency signal.

The CPU 84 inputs tuning control data for switching the frequency division ratios 1 / A and 1 / N (only one of them may be used) of the variable frequency dividers 14 and 16 to the phase synchronization circuit 1. The digital signal demodulation IC 82 performs various digital demodulation processes such as video detection and audio detection based on the intermediate frequency (IF) signal output from the IF amplifier 74. The digital signal demodulation IC 82 performs various digital demodulation processes based on the intermediate frequency (IF) signal output from the IF amplifier 74. The digital signal demodulation IC 82 detects the bit error rate of the digital signal detected during the digital demodulation processing corresponding to the phase noise of the oscillation circuit 26,
The detected bit error rate is input to the CPU 84. The CPU 84 controls the digital data V for controlling the operating current of the oscillation circuit 26 so that the bit error rate falls within a predetermined range (for example, below a predetermined value).
D is generated, and the generated digital data VD is input to the data converter 76 as bus data.

The data converter 76 uses the digital data VD
Is converted into an analog current control signal, and this current control signal is input to the current control input terminal 25 of the VCO 20. That is, the mixer unit 72, the IF amplifier 74, the data converter 7
6, the digital signal demodulation IC 82, and the CPU 84 constitute a phase noise monitoring unit according to the present invention.
The data converter 76 is not limited to the one that D / A converts the input digital data VD, but may be any one that can generate an analog current control signal corresponding to the digital data VD output from the CPU 84. . That is, CP
It suffices that there is a certain correlation between the digital data VD output from U84 and the current control signal converted by the data converter 76. The digital data VD is obtained by digitizing (A / D converting) an analog signal value. The data is not limited to the one obtained, and may be code data encoded under a predetermined rule. When the code data is used, the frequency division ratios 1 / A, 1 in the variable frequency dividers 14, 16 described later are used.
The setting of / N may also be performed via the data converter 76.

With the above configuration, the television system 3
Forms a PLL synthesizer type tuning circuit.
For example, the oscillation frequency of the reference oscillator 12 (reference frequency)
f1 is 3.58 MHz, the frequency division ratio of the variable frequency divider 14 is 1 / A
Is set to 1/3667. At this time, the tuner IC 70
Is the frequency f2 = 97 of 1/3667 of 3.58 MHz
6 Hz, local oscillation frequency 15 when receiving ch1
It matches 1 / (2400 * 64) of 0 MHz, and is 1 / (2 of local oscillation frequency 162 MHz when receiving ch3.
592 * 64), the phase-locked loop 1 works to adjust the local oscillation frequency to a predetermined frequency.

For example, it is assumed that the VCO 20 emits an output signal having a higher frequency as the voltage V1 applied to the frequency control input terminal 22 is higher. In this case, when a channel button (not shown) is pressed to receive “ch1”, “0” or “1”, the CPU 84 causes the one frequency control input terminal 23 of the frequency control unit 27 to apply VHF as the band switching voltage to the frequency control input terminal 23.
Apply a voltage to receive the low band and divide by 1
The tuning control data such that / N becomes 1 / (2400 * 64) is input to the variable frequency divider 16.

If the frequency f3 of the output signal of the oscillation circuit 26, which is the local oscillation frequency, is accurately held at the local oscillation frequency of 150 MHz when receiving ch1, the frequency f4 of the output signal of the variable frequency divider 16 becomes , "150 × 10
^ 6 × (1/64) × (1/2400) ≈976.56
Hz ”(“ ^ ”indicates exponentiation), and the phase comparator 1
It becomes equal to the frequency f2 of the reference signal having a constant frequency applied to the signal 8. The phase comparator 18 outputs a comparison output (detection output) of a reference value (eg, “0”) when f2 and f4 are equal to each other, and a value smaller than the reference value (eg, negative) when f2> f4. In this case, the output voltage V0 is larger than the reference value (for example, positive), and the output voltage V0 is applied to the loop filter circuit 30.

The loop filter circuit 30 includes the phase comparator 1
The voltage signal V0 from 8 is smoothed, and this smoothed voltage signal V1 is input to one frequency control input terminal 22 of the frequency controller 27. For example, when V0 is larger than the reference value, it drops below the reference voltage VS in proportion to its magnitude, and when V0 is smaller than the reference value, it rises above the reference voltage VS in proportion to its magnitude. The voltage signal V1 is input to the frequency control input terminal 22 as a frequency control signal. Therefore, the local oscillation frequency f3 is exactly 150M.
In the case of Hz, the voltage applied to the frequency control input terminal 22 becomes the voltage of the reference voltage VS (for example, 5V constant) so that the oscillation frequency becomes 150 MHz.
When the frequency is higher than MHz, the voltage applied to the frequency control input terminal 22 is reduced and the negative feedback operation is performed so as to reduce the oscillation frequency of the oscillation circuit 26.

As a result, a signal of a constant 150 MHz corresponding to ch1 as the local oscillation frequency f3 is input to the mixer 72 from the oscillation circuit 26. Therefore, from the mixer section 72, the frequency f5 (VHF band; 90-
222 MHz, UHF band; 470 to 770 MHz) and the oscillation frequency f3 of the oscillation circuit 26
The 57 MHz intermediate frequency signal for 1 is output, and the digital signal demodulation IC 82 can stably decode the ch1 digital television signal.

Next, when the channel button is pressed "0" or "3", the CPU 84 causes the frequency division ratio 1 / N to be 1 / (259).
Variable frequency divider 1 for tuning control data such that 2 * 64)
Enter in 6. Since the oscillation frequency f3 immediately before is 150 MHz, the frequency f4 of the output signal of the variable frequency divider 16 is "1.
50 × 10 ^ 6 × (1/64) × (1/2592) ≈9
Since 04 Hz ″ and f2> f4, the comparison output (detection output) of the phase comparator 18 becomes smaller than the reference value.

Therefore, the voltage applied to the frequency control input terminal 22 rises, and the local oscillation frequency operates so that the frequency is 162 MHz for receiving ch3. As a result, the frequency f5 (V
HF band: 90-222 MHz, UHF band: 470-77
0 MHz) and 57 MHz of the difference frequency between the oscillation frequency f3 of the oscillation circuit 26 for ch3 instead of ch1.
Intermediate frequency signal is output, and the digital signal demodulation IC 82
Can stably decode the ch3 digital television signal.

In the preceding example, ch1 and ch3 have been described, but not limited to this, ch1 to ch1 in the VHF band.
2 (190-222 MHz), ch1 for UHF band
3 to ch 62 (470 to 770 MHz). As described above, the television system 3 outputs the video and audio of the channel desired by the user by switching the local oscillation frequency, that is, the oscillation frequency of the oscillation circuit 26 over a wide band according to the pressed channel button. .

On the other hand, if the oscillating frequency of the oscillating circuit 26 is switched over a wide band while the operating current of the oscillating circuit 26 is kept constant, as described above, even if low phase noise occurs at a certain oscillating frequency, the VHF band (1 ~ 12CH; 90-22
2MHz) or UHF band (13 to 62CH; 470)
.About.770 MHz), low phase noise cannot be made over a wide range of tuning frequency bands. However, in the television system 3 having the above configuration, the bit error rate of the digital signal detected at the time of digital demodulation processing is detected, feedback is given to the VCO 20, and the VC
The operating current of O (in particular, the oscillation circuit 26) is automatically set to an optimum current value.

For example, when the bit error rate detected during the digital demodulation processing in the digital signal demodulation IC 82 exceeds a predetermined level, the CPU 84
The digital data VD is reset so that the value of the current control signal after the data conversion by the data converter 76 becomes higher. As a result, the amount of current flowing through the variable current source 29a increases, the operating current of the oscillation circuit 26 increases, and the phase noise of f3 decreases. If the phase noise is reduced,
The bit error rate also becomes small and is below a predetermined level.

As described above, since the bit error rate is correlated with the phase noise of the oscillation circuit 26, the operating current value of the oscillation circuit 26 is automatically optimized by detecting the bit error rate with the digital signal demodulation IC 82 (previous example). Then, it becomes possible to obtain low phase noise by setting it to a predetermined level or lower). In digital signal processing, since the monitoring of the bit error rate can be easily realized, the phase noise detection method is also simplified. For example, when the phase noise characteristic with respect to the oscillation frequency of the oscillator circuit 26 is not a monotone increase or a monotone decrease, the control digital data V
An optimum amount of current that minimizes phase noise can be set by searching and setting a VD value that minimizes the bit error rate detected by sequentially varying D. This makes it possible to easily and surely solve the problem of deterioration of phase noise, which is the most important characteristic of the digital TV.

In the above description, the operating current of the oscillation circuit 26 is controlled to increase when the bit error rate becomes equal to or higher than a predetermined level. However, according to the value of the bit error rate, the oscillation circuit 26 operates. The operating current amount may be controlled in multiple stages or continuously, and the feedback control may be dynamically performed so that the phase noise is always in a predetermined range or a predetermined value.

In addition, a data converter 76 is provided in the tuner IC 70, and the digital data VD output from the CPU 84 is converted into an analog current control signal by the data converter 76 and then applied to the current control input terminal 25. However, the tuner IC has the same configuration as that shown in FIG.
An analog current control signal may be applied to the current control input terminal 25 from the outside of 70.

Although the present invention has been described using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. Various changes or improvements can be added to the above-described embodiment, and a mode in which such changes or improvements are added is also included in the technical scope of the present invention. Also,
The above embodiments do not limit the claimed invention, and all combinations of the features described in the embodiments are not necessarily essential to the solution of the invention.

For example, in the above embodiment, the phase noise level is determined by detecting the jitter (frequency fluctuation) of the oscillation circuit output f3, the bit error rate of the digital signal, and the like, which are examples of information corresponding to the phase noise. However, the phase noise can be detected using other detection methods such as directly detecting the phase noise or indirectly detecting the phase noise by detecting predetermined information corresponding to the phase noise. You may judge. For example, since the output signal of the phase comparator 18 directly represents the phase noise (phase unevenness) of the oscillation circuit output f3, the degree of variation of the output signal of the phase comparator 18 is monitored and as described in the above embodiment. You may perform various controls. Alternatively, in the case of a configuration for performing digital signal processing like the digital signal demodulation IC 82, since the area of the opening portion in the eye pattern of the digital signal represents phase noise, the degree of variation in the area of the opening portion is monitored, The control as described in the above embodiment may be performed.

Further, the present invention can be applied to an oscillator in which the phase noise fluctuates depending on the operating current or all circuits and devices having this oscillator, and what is the configuration of the oscillator circuit (resonant circuit) that constitutes the oscillator? May be For example, in the embodiment shown in FIG. 5, a television system equipped with a PLL frequency synthesizer type tuning mechanism (tuning mechanism) using a phase locked loop has been described as an example. The present invention can also be applied to a communication device for reception or transmission provided with a phase synchronization circuit such as a wireless device or a mobile phone (for example, a W-CDMA system that requires wideband transmission / reception characteristics). Further, the present invention is not limited to communication equipment, and can be applied to other devices that use a phase-locked loop and are used over a predetermined frequency range (two frequencies relatively separated may be used). For example, the present invention can be applied to general angle modulation circuits, angle demodulation circuits, and devices equipped with these circuits. Of course, the present invention can be applied not only to the phase locked loop circuit but also to a device used as an oscillator alone.

The current control signal for controlling the operating current of the oscillation circuit is not limited to the voltage signal and may be a current signal. In this case, the switch SW1 (FIGS. 1 and 2) and the variable current source 29a (FIGS. 3 and 4) may be provided with a current input terminal as an interface portion thereof. Further, if necessary, a function part for current / voltage conversion or vice versa may be provided.

[0063]

As described above, according to the present invention, the operating current of the oscillating circuit can be changed. Therefore, the operating current of the oscillating circuit can be changed over that of the conventional oscillator having the fixed operating current. It becomes possible to obtain low phase noise over a wider oscillation frequency band. Then, various circuits and devices having such an oscillator can solve the problem of phase noise over a wide frequency band.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an oscillator according to the invention.

FIG. 2 is a block diagram showing an embodiment of a phase locked loop circuit having the oscillator shown in FIG.

FIG. 3 is a diagram showing a modification of the phase locked loop circuit shown in FIG.

FIG. 4 is a diagram showing another modification of the phase synchronization circuit.

FIG. 5 is a block diagram showing an example of a television system including a tuner having a VCO.

FIG. 6 is a diagram showing a conventional technique, and is a block diagram (A) showing a basic configuration of a phase synchronization circuit and a circuit diagram showing a conventional example of an oscillator in the phase synchronization circuit.

[Explanation of symbols]

1 ... Phase synchronization circuit, 3 ... Television system, 10 ...
PLLIC, 12 ... Reference oscillator, 14, 16 ... Variable frequency divider, 18 ... Phase comparator, 20 ... VCO, 22 ... Frequency control input terminal, 24 ... Output terminal, 25 ... Current control input terminal, 26 ... Oscillation circuit, 27 ... Frequency control circuit, 28 ... Current source unit, 29 ... Current switching circuit, 29a ... Variable current source, 3
0 ... Loop filter circuit, 70 ... Tuner IC, 72 ...
Mixer section, 74 ... IF amplifier, 76 ... Data converter, 8
0 ... High frequency signal receiving circuit, 82 ... Digital signal demodulation I
C, 84 ... CPU, 90, 92 ... Jitter amount monitoring circuit, S
W1 ... Switch, VT21 ... Reference voltage source

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Claims (10)

[Claims] 1. An oscillating circuit that oscillates at a predetermined frequency, a frequency control circuit that controls the oscillating frequency of the oscillating circuit based on an input frequency control signal, and the oscillating circuit based on an input current control signal. And an operating current control circuit for controlling the operating current of the oscillator. 2. An oscillator having a frequency control input terminal, which generates an output signal of a first frequency corresponding to the frequency control signal input to the frequency control input terminal, and a reference of a second frequency serving as a reference. A phase comparator that compares the phase of a signal and a compared signal corresponding to the first frequency, and an output signal of the phase comparator is smoothed, and the smoothed signal is used as the frequency control signal of the oscillator. A phase locked loop circuit including a loop filter unit applied to a frequency control input terminal, wherein the oscillator is based on an oscillation circuit that oscillates at a predetermined frequency and the frequency control signal input to the frequency control input terminal. A frequency control circuit that controls the oscillation frequency of the oscillation circuit, a current control input terminal, and a current control signal based on a current control signal input to the current control input terminal. Phase locked loop circuit characterized by comprising an operation current control circuit for controlling the work current. 3. A current control unit for generating the current control signal based on a frequency of an output signal output from the oscillator, and applying the generated current control signal to the current control input terminal. The phase locked loop circuit according to claim 2. 4. The phase noise of the output signal output from the oscillator is detected, the current control signal is generated based on the detected phase noise, and the generated current control signal is applied to the current control input terminal. 3. The phase locked loop circuit according to claim 2, further comprising a phase noise monitoring unit that operates. 5. A digital signal processing unit for generating a digital signal to be processed based on an output signal output from the oscillator and another signal different from the output signal, wherein the phase noise monitoring unit is provided. The phase lock circuit according to claim 4, wherein the phase noise is detected by detecting a bit error rate of a digital signal to be processed generated by the digital signal processing unit. 6. A phase synchronization including an oscillator circuit, a current control input terminal, and an oscillator having an operating current control circuit for controlling an operating current of the oscillation circuit based on a current control signal input to the current control input terminal. A circuit, and a current controller that generates the current control signal based on the frequency of the output signal output from the oscillation circuit and applies the generated current control signal to the current control input terminal. Tuning device to do. 7. A phase synchronization comprising an oscillator circuit, a current control input terminal, and an oscillator having an operating current control circuit for controlling an operating current of the oscillator circuit based on a current control signal input to the current control input terminal. Circuit and the phase noise of the output signal output from the oscillation circuit is detected, the current control signal is generated based on the detected phase noise, and the generated current control signal is applied to the current control input terminal. A tuning device comprising: a phase noise monitoring unit. 8. A receiving unit for receiving a communication signal, wherein the phase synchronization circuit compares the phase of a received wave received by the receiving unit with an output signal output from the oscillating circuit. Item 8. A tuning device according to Item 6 or 7. 9. A digital signal processing unit that generates a digital signal to be processed based on an output signal output from the oscillator and a received signal received by the receiving unit, wherein the phase noise monitoring unit includes the digital signal processing unit. The tuning device according to claim 7, wherein the phase noise is detected by detecting a bit error rate of a digital signal to be processed generated by the signal processing unit. 10. The tuning device according to claim 6, wherein the receiving unit receives a television signal as the communication signal.