JPS604025U - tuning device - Google Patents
tuning deviceInfo
- Publication number
- JPS604025U JPS604025U JP9410783U JP9410783U JPS604025U JP S604025 U JPS604025 U JP S604025U JP 9410783 U JP9410783 U JP 9410783U JP 9410783 U JP9410783 U JP 9410783U JP S604025 U JPS604025 U JP S604025U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- transistor
- tuner
- diode
- limiting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の同調装置の一例を示す回路図であり、特
に受信バンドの下側の周波数が制限される同調装置を示
している。第２図はこの考案の一実施例の回路図であり
、特に受信バンドの下側の周波数が制限される同調装置
の例を示している。
第３図はこの考案の他の実施例を示す回路図であり、特
に受信バンドの上側の周波数が制限される同調装置の例
を示している。
図において、１はバンド切換信号印加端子、２はスイッ
チング用トランジスタ、３は電源端子、４は分圧用固定
抵抗、５は電圧調整用可変抵抗器、６（゛よ逆流阻止用
ダイオード、７は保護用抵抗、８はチューナ、９は可変
電圧源１０の出力インピーダンス、１０は可変電圧源、
１１はエミッタ抵抗、１２はＰＮＰ形のトランジスタ、
１３はＮＰＮ形のトランジスタを示す。FIG. 1 is a circuit diagram showing an example of a conventional tuning device, and particularly shows a tuning device in which frequencies on the lower side of the receiving band are limited. FIG. 2 is a circuit diagram of one embodiment of this invention, and particularly shows an example of a tuning device in which the lower frequencies of the receiving band are limited. FIG. 3 is a circuit diagram showing another embodiment of the present invention, and particularly shows an example of a tuning device in which the upper frequency of the reception band is limited. In the figure, 1 is a band switching signal application terminal, 2 is a switching transistor, 3 is a power supply terminal, 4 is a fixed resistor for voltage division, 5 is a variable resistor for voltage adjustment, 6 is a reverse current blocking diode, and 7 is a protection 8 is the tuner, 9 is the output impedance of the variable voltage source 10, 10 is the variable voltage source,
11 is an emitter resistor, 12 is a PNP type transistor,
13 indicates an NPN type transistor.
Claims (1)
電圧発生手段と、前記チューニング電圧に応じてその受
信周波数が変化するチューナと、前記チューナの受信周
波数を制限するために前記チューニング電圧に重畳され
る所定の電圧を発生する受信周波数制限用電圧発生手段
と、前記受信周波数制限用電圧発生手段と前記チューナ
との間に介挿されるダイオードとを含む同調装置におい
て、 前記受信周波数制限用電圧発生手段の出力電圧をベース
入力として受け、かつそのエミッタ出力が前記ダイオー
ドに与えられてコレクタ接地回路を構成するトランジス
タを備え、前記トランジスタのベース−エミッタ間の温
度特性で前記ダイオードの温度特性を打消すよ゛ う
にしたことを特徴とする、同調装置。 （２）前記受信周波数制限用電圧発生手段は、前記チュ
ーナの受信バンドの下側の受信周波数を制限するための
電圧を発生する手段を含み、前記ダイオードは、そのア
ノードが前記トランジスタのエミッタに接続され、その
カソードが前記チューナに接続され、 前記トランジスタの極性はＰＮＰ形に選ばれている、実
用新案登録請求の範囲第１項記載の同調装置。 （３）前記受信周波数制限用電圧発生手段は、前記チュ
ーナの受信バンドの上限周波数を制限するための電圧を
発生する手段を含み、 前記ダイオードは、そのカソードが前記トランジスタの
エミッタに接続され、そのアノードが前記チューナに接
続され、 前記トランジスタの極性はＮＰＮ形に選ばれている、実
用新案登録請求の範囲第１項記載の同調装置。[Claims for Utility Model Registration] (1) A tuning voltage generating means for generating a tuning voltage, a tuner whose receiving frequency changes according to the tuning voltage, and a tuning device for limiting the receiving frequency of the tuner. A tuning device including a receiving frequency limiting voltage generating means for generating a predetermined voltage to be superimposed on a voltage, and a diode inserted between the receiving frequency limiting voltage generating means and the tuner, a transistor which receives the output voltage of the voltage generating means as a base input and whose emitter output is applied to the diode to constitute a common collector circuit, and the temperature characteristic between the base and emitter of the transistor is the temperature characteristic of the diode. A tuning device characterized by being designed to cancel out. (2) The receiving frequency limiting voltage generating means includes means for generating a voltage for limiting the receiving frequency below the receiving band of the tuner, and the anode of the diode is connected to the emitter of the transistor. The tuning device according to claim 1, wherein the transistor has a cathode connected to the tuner, and the polarity of the transistor is selected as PNP type. (3) The receiving frequency limiting voltage generating means includes means for generating a voltage for limiting the upper limit frequency of the receiving band of the tuner, and the diode has a cathode connected to the emitter of the transistor, and the diode has a cathode connected to the emitter of the transistor. The tuning device according to claim 1, wherein an anode is connected to the tuner, and the polarity of the transistor is selected as NPN type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9410783U JPS604025U (en) | 1983-06-17 | 1983-06-17 | tuning device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9410783U JPS604025U (en) | 1983-06-17 | 1983-06-17 | tuning device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS604025U true JPS604025U (en) | 1985-01-12 |
| JPH0119466Y2 JPH0119466Y2 (en) | 1989-06-06 |
Family
ID=30225427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9410783U Granted JPS604025U (en) | 1983-06-17 | 1983-06-17 | tuning device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS604025U (en) |
-
1983
- 1983-06-17 JP JP9410783U patent/JPS604025U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0119466Y2 (en) | 1989-06-06 |
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