JPS6085452U - wireless receiver - Google Patents

wireless receiver

Info

Publication number
JPS6085452U
JPS6085452U JP1983177444U JP17744483U JPS6085452U JP S6085452 U JPS6085452 U JP S6085452U JP 1983177444 U JP1983177444 U JP 1983177444U JP 17744483 U JP17744483 U JP 17744483U JP S6085452 U JPS6085452 U JP S6085452U
Authority
JP
Japan
Prior art keywords
circuit
synthesizer
wireless receiver
switched
radio receiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983177444U
Other languages
Japanese (ja)
Inventor
鈴鹿　和男
Original Assignee
日立電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立電子株式会社 filed Critical 日立電子株式会社
Priority to JP1983177444U priority Critical patent/JPS6085452U/en
Publication of JPS6085452U publication Critical patent/JPS6085452U/en
Pending legal-status Critical Current

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  • Transceivers (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来技術による無線受信機のブロック図、第２
図は本考案の一実施例のブロック図。 １６：周波数シンセサイザ、２１：固定局発回路、１５
：チャネル制御回路、１７：第１局発切替回路、１８：
電源切替回路。Figure 1 is a block diagram of a wireless receiver according to the prior art, Figure 2 is a block diagram of a wireless receiver according to the prior art;
The figure is a block diagram of one embodiment of the present invention. 16: Frequency synthesizer, 21: Fixed station oscillation circuit, 15
: Channel control circuit, 17: First station switching circuit, 18:
Power switching circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 多チヤンネルシンセサイザ式無線受信機において、周波
数シンセサイザ、チャネル制御回路、水晶発振回路とそ
の出力のてい倍回路をもち、前記周波数シンセサイザと
前記てい倍回路の出力をチャネル制御回路によって切替
えて混合回路に供給し、併せて前記シンセサイザと前記
水晶発振回路、てい倍回路に供給する電源を切替えるこ
とを特徴とした無線受信機。A multi-channel synthesizer type radio receiver has a frequency synthesizer, a channel control circuit, a crystal oscillation circuit, and an output multiplication circuit, and the outputs of the frequency synthesizer and multiplication circuit are switched by the channel control circuit and supplied to the mixing circuit. The radio receiver is further characterized in that the power supply to the synthesizer, the crystal oscillation circuit, and the multiplier circuit is switched.
JP1983177444U 1983-11-18 1983-11-18 wireless receiver Pending JPS6085452U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983177444U JPS6085452U (en) 1983-11-18 1983-11-18 wireless receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983177444U JPS6085452U (en) 1983-11-18 1983-11-18 wireless receiver

Publications (1)

Publication Number Publication Date
JPS6085452U true JPS6085452U (en) 1985-06-12

Family

ID=30385499

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983177444U Pending JPS6085452U (en) 1983-11-18 1983-11-18 wireless receiver

Country Status (1)

Country Link
JP (1) JPS6085452U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08317001A (en) * 1995-05-24 1996-11-29 Nec Corp Digital modulation/demodulation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08317001A (en) * 1995-05-24 1996-11-29 Nec Corp Digital modulation/demodulation circuit

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