JPS5939548U - synthesizer receiver - Google Patents
synthesizer receiverInfo
- Publication number
- JPS5939548U JPS5939548U JP13568882U JP13568882U JPS5939548U JP S5939548 U JPS5939548 U JP S5939548U JP 13568882 U JP13568882 U JP 13568882U JP 13568882 U JP13568882 U JP 13568882U JP S5939548 U JPS5939548 U JP S5939548U
- Authority
- JP
- Japan
- Prior art keywords
- muting
- synthesizer receiver
- comparison
- level
- synthesizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の一実施例におけるシンセサイザ受信機の
回路ブロック図である。
１・・・フロントエンド、２・・・第１の中間周波数増
幅器、３・・・第２の中間周波数増幅器、４・・−ＦＭ
復調器、５・・・低周波数増幅器、６・・・ミューティ
ング回路、７・・・アナログ・ディジタル変換器、８・
・・マイクロプロセッサ、９・・・ミューティングレベ
ル切換手段。The drawing is a circuit block diagram of a synthesizer receiver in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Front end, 2...1st intermediate frequency amplifier, 3...2nd intermediate frequency amplifier, 4...-FM
demodulator, 5... low frequency amplifier, 6... muting circuit, 7... analog-digital converter, 8.
...Microprocessor, 9...Muting level switching means.
Claims (1)
ングレベル設定手段により設定されたミューティングレ
ベルを記憶するメモリ手段と、このメモリ手段の記憶内
容と受信電波レベルとを比較する比較手段と、この比較
手段の出力に応じてミューティング回路を制御する制御
手段とを備えたシンセサイザ受信機。 ２ 設定されたミューティングレベルを表示する表示手
段を備えた実用新案登録請求の範囲第１項記載のシンセ
サイザ受信機。[Scope of Claim for Utility Model Registration] ■ A muting level setting means, a memory means for storing the muting level set by the muting level setting means, and a comparison between the stored contents of the memory means and the received radio wave level. A synthesizer receiver comprising a comparison means and a control means for controlling a muting circuit according to the output of the comparison means. 2. A synthesizer receiver according to claim 1, which is equipped with a display means for displaying a set muting level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13568882U JPS5939548U (en) | 1982-09-06 | 1982-09-06 | synthesizer receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13568882U JPS5939548U (en) | 1982-09-06 | 1982-09-06 | synthesizer receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5939548U true JPS5939548U (en) | 1984-03-13 |
Family
ID=30305331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13568882U Pending JPS5939548U (en) | 1982-09-06 | 1982-09-06 | synthesizer receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5939548U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04119141U (en) * | 1991-04-11 | 1992-10-26 | アイコム株式会社 | wireless communication device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52127114A (en) * | 1976-04-19 | 1977-10-25 | Hitachi Ltd | Muting circuit |
-
1982
- 1982-09-06 JP JP13568882U patent/JPS5939548U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52127114A (en) * | 1976-04-19 | 1977-10-25 | Hitachi Ltd | Muting circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04119141U (en) * | 1991-04-11 | 1992-10-26 | アイコム株式会社 | wireless communication device |
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