JPS5963535U - synthesizer receiver - Google Patents

synthesizer receiver

Info

Publication number
JPS5963535U
JPS5963535U JP15942582U JP15942582U JPS5963535U JP S5963535 U JPS5963535 U JP S5963535U JP 15942582 U JP15942582 U JP 15942582U JP 15942582 U JP15942582 U JP 15942582U JP S5963535 U JPS5963535 U JP S5963535U
Authority
JP
Japan
Prior art keywords
synthesizer receiver
reference level
synthesizer
storing
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15942582U
Other languages
Japanese (ja)
Inventor
弘 古賀
Original Assignee
松下電器産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電器産業株式会社 filed Critical 松下電器産業株式会社
Priority to JP15942582U priority Critical patent/JPS5963535U/en
Publication of JPS5963535U publication Critical patent/JPS5963535U/en
Pending legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図面は本考案の一実施例のブロック図である。 １はフロントエンド、２は第１の中間周波数増幅器、３
は第２の中間周波数増幅器、４はアナログ・デジタル変
換器、５はマイクロプロセッサ、。 ６は基準レベルの選択手段、７は表示器。The drawing is a block diagram of an embodiment of the present invention. 1 is the front end, 2 is the first intermediate frequency amplifier, 3
is a second intermediate frequency amplifier, 4 is an analog-to-digital converter, and 5 is a microprocessor. 6 is a reference level selection means, and 7 is a display.

Claims (3)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）受信周波数コードを記憶するメモリと、受信信号
レベルにより記憶・非記憶動作を判定する判定手段とを
備え、前記判定を行う基準となる選定された基準レベル
コードをメモリに記憶する構成としたシンセサイザ受信
器。(1) A configuration comprising a memory for storing a reception frequency code and a determination means for determining storage/non-storage operation based on the reception signal level, and storing in the memory a selected reference level code that serves as a reference for making the determination. synthesizer receiver. （２）前記基準レベルコードが複数個設定され、それら
の内の任意のものを選定する構成とした実用新案登録請
求の範囲第１項に記載のシンセサイザ受信器。(2) The synthesizer receiver according to claim 1, wherein a plurality of the reference level codes are set and any one of them is selected. （３）選定された基準レベルコードを表示する表示器が
設けられた実用新案登録請求の範囲第１項に記載のシン
セサイザ受信器。(3) The synthesizer receiver according to claim 1, which is provided with a display that displays the selected reference level code.
JP15942582U 1982-10-20 1982-10-20 synthesizer receiver Pending JPS5963535U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15942582U JPS5963535U (en) 1982-10-20 1982-10-20 synthesizer receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15942582U JPS5963535U (en) 1982-10-20 1982-10-20 synthesizer receiver

Publications (1)

Publication Number Publication Date
JPS5963535U true JPS5963535U (en) 1984-04-26

Family

ID=30350945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15942582U Pending JPS5963535U (en) 1982-10-20 1982-10-20 synthesizer receiver

Country Status (1)

Country Link
JP (1) JPS5963535U (en)

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