JPS63113341U - - Google Patents
Info
- Publication number
- JPS63113341U JPS63113341U JP1987004595U JP459587U JPS63113341U JP S63113341 U JPS63113341 U JP S63113341U JP 1987004595 U JP1987004595 U JP 1987004595U JP 459587 U JP459587 U JP 459587U JP S63113341 U JPS63113341 U JP S63113341U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- detection signal
- output
- priority
- detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 11
- 238000012544 monitoring process Methods 0.000 claims 1
- 239000003550 marker Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Description
第1図は本考案の一実施例を示したブロツク図
、第2図は第1図実施例の動作を示すタイムチヤ
ートである。
1……FM復調器、2……TEST盤、3……
正規の表示情報マーカー検出回路、4……擬似表
示情報マーカー検出回路、5……インバータ回路
、6……ナンド回路、7……フリツプ・フロツプ
回路、8……セレクター回路、9……シリアルー
パラレル変換回路、10……試験中信号入力回路
、11……共通処理部。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the embodiment shown in FIG. 1...FM demodulator, 2...TEST board, 3...
Regular display information marker detection circuit, 4... pseudo display information marker detection circuit, 5... inverter circuit, 6... NAND circuit, 7... flip-flop circuit, 8... selector circuit, 9... serial-parallel Conversion circuit, 10... Signal input circuit under test, 11... Common processing section.
Claims (1)
第1の検出信号を出力する第1の検出回路と、擬
似表示情報に含まれる第2の識別符号を検出して
第2の検出信号を出力する第2の検出回路と、前
記第1の検出信号と第2の検出信号を監視して第
1の検出信号を判別したときに優先信号を出力す
る優先信号出力手段と、前記受信情報と擬似表示
情報を入力して前記優先信号が得られたときに前
記受信情報を優先的に選択して出力するとともに
前記第2の検出信号だけが得られたときに前記擬
似表示情報を出力する選択手段と、該選択手段の
出力信号を処理して表示する信号処理手段とを設
けたことを特徴とする受信情報優先回路。 a first detection circuit that detects a first identification code included in the received information and outputs a first detection signal; and a first detection circuit that detects a second identification code included in the pseudo display information and outputs a second detection signal. a second detection circuit for outputting, a priority signal output means for monitoring the first detection signal and the second detection signal and outputting a priority signal when the first detection signal is determined; and the reception information Selecting to preferentially select and output the received information when pseudo display information is input and the priority signal is obtained, and output the pseudo display information when only the second detection signal is obtained. 1. A received information priority circuit comprising: means for processing and displaying an output signal of said selection means.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987004595U JPS63113341U (en) | 1987-01-14 | 1987-01-14 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987004595U JPS63113341U (en) | 1987-01-14 | 1987-01-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63113341U true JPS63113341U (en) | 1988-07-21 |
Family
ID=30785398
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987004595U Pending JPS63113341U (en) | 1987-01-14 | 1987-01-14 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63113341U (en) |
-
1987
- 1987-01-14 JP JP1987004595U patent/JPS63113341U/ja active Pending
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