JPS6293233U - - Google Patents
Info
- Publication number
- JPS6293233U JPS6293233U JP18282185U JP18282185U JPS6293233U JP S6293233 U JPS6293233 U JP S6293233U JP 18282185 U JP18282185 U JP 18282185U JP 18282185 U JP18282185 U JP 18282185U JP S6293233 U JPS6293233 U JP S6293233U
- Authority
- JP
- Japan
- Prior art keywords
- input device
- signal
- line
- space
- transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 4
- 230000008054 signal transmission Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 9
- 238000005070 sampling Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
Landscapes
- Input From Keyboards Or The Like (AREA)
Description
第１図は入力装置と本体側からくる信号を処理
するキー入力ＣＥの回路構成図、第２図は入力装
置を含む情報処理装置における一般的な外観構成
を示す斜視図、第３図は第２図に示す構成を布線
系よりみたブロツク図、第４図は第３図に示す主
制御回路の構成を示すブロツク図、第５図ａはデ
ータのシリアル転送を示すフオーマツト図、第５
図ｂは前記シリアル転送におけるデータのサンプ
リングのタイミングを示す図、第６図はタイマＩ
Ｃの動作説明図、第７図は入力装置に異常があつ
た場合にキー入力ＣＥ側より入力装置を初期化す
る動作タイミングを示す図である。
３……入力装置、１６……キー入力ＣＥ、３０
……処理ＩＣ、３１……ＯＲ型バツフア素子、３
２……信号線、３３……演算ＬＳＩ、３４……バ
ツフア素子、３５……レシーバ素子、３６……セ
レクタ回路、３７……デコーダ回路、３８……ス
イツチマトリクス、４５……レシーバ素子。
Fig. 1 is a circuit configuration diagram of a key input CE that processes signals coming from the input device and the main body side, Fig. 2 is a perspective view showing the general external configuration of an information processing device including the input device, and Fig. 3 is a circuit diagram of a key input CE that processes signals coming from the input device and the main body side. 2 is a block diagram of the configuration shown in the wiring system; FIG. 4 is a block diagram showing the configuration of the main control circuit shown in FIG. 3; FIG. 5a is a format diagram showing serial data transfer;
Figure b is a diagram showing the timing of data sampling in the serial transfer, and Figure 6 is a diagram showing the timing of data sampling in the serial transfer.
FIG. 7, which is an explanatory diagram of operation C, is a diagram showing the operation timing for initializing the input device from the key input CE side when an abnormality occurs in the input device. 3...Input device, 16...Key input CE, 30
... Processing IC, 31 ... OR type buffer element, 3
2... Signal line, 33... Arithmetic LSI, 34... Buffer element, 35... Receiver element, 36... Selector circuit, 37... Decoder circuit, 38... Switch matrix, 45... Receiver element.
Claims (1)
の信号を処理する処理装置間を少なくとも３本の
配線で結合し、該配線のうち少なくとも１本を信
号用として使用し、該信号線上でマーク、スペー
スの２つの状態を有し信号の送信あるいは受信が
無い場合はマークとなるような信号を用いて、相
互にデータの転送をするよう構成された信号伝送
方式において、該処理装置は、該信号線上を一定
基準データの転送に要する時間より長い期間スペ
ースに保守する手段を有し、該入力装置は、該信
号線上に対してスペースとなつている期間を計測
する手段を有し、一定基準データの転送に要する
時間より長い場合は、該入力装置の主回路を強制
的にリセツトする手段を有することにより、デー
タ信号線を用いるのみで、該処理装置が、該入力
装置を強制的にリセツトすることができることを
特徴とした信号伝送方式。 An input device having a plurality of contacts and a processing device that processes signals from the input device are connected by at least three wires, at least one of the wires is used for a signal, and a mark is placed on the signal wire. In a signal transmission system configured to mutually transfer data using a signal that has two states of space and becomes a mark when no signal is transmitted or received, the processing device The input device has means for maintaining a space on the line for a period longer than the time required to transfer constant reference data, and the input device has means for measuring a period of time when the line is a space with respect to the signal line, If the time is longer than the time required to transfer the input device, the processing device can forcibly reset the input device by simply using the data signal line by having means for forcibly resetting the main circuit of the input device. A signal transmission method characterized by the ability to
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18282185U JPS6293233U (en) | 1985-11-29 | 1985-11-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18282185U JPS6293233U (en) | 1985-11-29 | 1985-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6293233U true JPS6293233U (en) | 1987-06-15 |
Family
ID=31128976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18282185U Pending JPS6293233U (en) | 1985-11-29 | 1985-11-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6293233U (en) |
-
1985
- 1985-11-29 JP JP18282185U patent/JPS6293233U/ja active Pending
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