JPS6292653U - - Google Patents

Info

Publication number
JPS6292653U
JPS6292653U JP18463985U JP18463985U JPS6292653U JP S6292653 U JPS6292653 U JP S6292653U JP 18463985 U JP18463985 U JP 18463985U JP 18463985 U JP18463985 U JP 18463985U JP S6292653 U JPS6292653 U JP S6292653U
Authority
JP
Japan
Prior art keywords
wiring board
lead frame
land portion
hybrid
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18463985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18463985U priority Critical patent/JPS6292653U/ja
Publication of JPS6292653U publication Critical patent/JPS6292653U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図乃至第３図は本考案に係るハイブリツド
ＩＣの一実施例を説明するためのもので、第１図
はリードフレームのランド部上に固着される配線
基板積層体の分解斜視図、第２図は第１図の組立
完了斜視図、第３図は配線基板積層体に電子部品
を固着マウントしワイヤボンデイングした状態を
示す断面図である。第４図乃至第６図は本考案の
他の実施例を示す分解斜視図、組立完了斜視図、
断面図である。第７図乃至第９図はハイブリツド
ＩＣの従来例を説明するためのもので、第７図は
リードフレームのランド部上に固着される配線基
板を示す分解斜視図、第８図は配線基板上に電子
部品を固着マウントしワイヤボンデイングした状
態を示す斜視図、第９図は第８図の断面図である
。 １２……リードフレーム、１４……ランド部、
１６……配線基板積層体、１６ａ，１６ｂ，１６
ｃ……配線基板、２１ａ，２１ｂ，２１ｃ……凹
部、２２ａ，２２ｂ……半導体ペレツト。 1 to 3 are for explaining one embodiment of a hybrid IC according to the present invention, and FIG. 1 is an exploded perspective view of a wiring board stack fixed on a land portion of a lead frame, and FIG. 2 is a perspective view of the completed assembly of FIG. 1, and FIG. 3 is a sectional view showing a state in which electronic components are firmly mounted on the wiring board laminate and wire bonded. 4 to 6 are exploded perspective views and assembled perspective views showing other embodiments of the present invention,
FIG. 7 to 9 are for explaining conventional examples of hybrid ICs. FIG. 7 is an exploded perspective view showing a wiring board fixed on the land portion of a lead frame, and FIG. FIG. 9 is a perspective view showing a state in which electronic components are firmly mounted and wire bonded. FIG. 9 is a sectional view of FIG. 8. 12...Lead frame, 14...Land portion,
16... Wiring board laminate, 16a, 16b, 16
c... Wiring board, 21a, 21b, 21c... Recessed portion, 22a, 22b... Semiconductor pellet.

Claims (1)

【実用新案登録請求の範囲】 リードフレームのランド部上に配線基板を固着
すると共に、該配線基板上に複数の半導体ペレツ
トを含む電子部品を固着マウントしてなるハイブ
リツドＩＣにおいて、 複数の配線基板からなり、且つ、上記電子部品
の厚みと対応する深さを有する凹部が形成された
配線基板積層体を、リードフレームのランド部上
に固着し、配線基板積層体の各凹部に、それと対
応する電子部品を収納配置したことを特徴とする
ハイブリツドＩＣ。[Scope of Claim for Utility Model Registration] In a hybrid IC in which a wiring board is fixed on the land portion of a lead frame and electronic components including a plurality of semiconductor pellets are fixedly mounted on the wiring board, from a plurality of wiring boards. A wiring board laminate having a recess formed therein and having a depth corresponding to the thickness of the electronic component is fixed onto the land portion of the lead frame, and a corresponding electronic part is placed in each recess of the wiring board laminate. A hybrid IC characterized by a storage arrangement of parts.
JP18463985U 1985-11-29 1985-11-29 Pending JPS6292653U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18463985U JPS6292653U (en) 1985-11-29 1985-11-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18463985U JPS6292653U (en) 1985-11-29 1985-11-29

Publications (1)

Publication Number Publication Date
JPS6292653U true JPS6292653U (en) 1987-06-13

Family

ID=31132508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18463985U Pending JPS6292653U (en) 1985-11-29 1985-11-29

Country Status (1)

Country Link
JP (1) JPS6292653U (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0232558A (en) * 1988-06-02 1990-02-02 Burr Brown Corp Resin-sealed multi-chip hybrid integrated circuit
JPH0269967A (en) * 1988-09-05 1990-03-08 Nippon Telegr & Teleph Corp <Ntt> Package for high speed/high frequency integrated circuit
JPH036096A (en) * 1989-06-02 1991-01-11 Matsushita Electric Works Ltd Circuit board
JPH03198355A (en) * 1989-12-26 1991-08-29 Nec Corp Semiconductor device
JPH03268351A (en) * 1990-03-16 1991-11-29 Toshiba Corp Semiconductor device
JPH09199528A (en) * 1996-01-22 1997-07-31 Nec Corp Resin-sealed semiconductor device
JP2009176825A (en) * 2008-01-22 2009-08-06 Asmo Co Ltd Resin packaged semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492866A (en) * 1972-04-21 1974-01-11
JPS577148A (en) * 1980-06-16 1982-01-14 Mitsubishi Electric Corp Semiconductor module
JPS60189958A (en) * 1984-03-09 1985-09-27 Nec Kansai Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492866A (en) * 1972-04-21 1974-01-11
JPS577148A (en) * 1980-06-16 1982-01-14 Mitsubishi Electric Corp Semiconductor module
JPS60189958A (en) * 1984-03-09 1985-09-27 Nec Kansai Ltd Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0232558A (en) * 1988-06-02 1990-02-02 Burr Brown Corp Resin-sealed multi-chip hybrid integrated circuit
JPH0269967A (en) * 1988-09-05 1990-03-08 Nippon Telegr & Teleph Corp <Ntt> Package for high speed/high frequency integrated circuit
JPH036096A (en) * 1989-06-02 1991-01-11 Matsushita Electric Works Ltd Circuit board
JPH03198355A (en) * 1989-12-26 1991-08-29 Nec Corp Semiconductor device
JPH03268351A (en) * 1990-03-16 1991-11-29 Toshiba Corp Semiconductor device
JPH09199528A (en) * 1996-01-22 1997-07-31 Nec Corp Resin-sealed semiconductor device
JP2009176825A (en) * 2008-01-22 2009-08-06 Asmo Co Ltd Resin packaged semiconductor device

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