JPH03198355A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03198355A JPH03198355A JP33969889A JP33969889A JPH03198355A JP H03198355 A JPH03198355 A JP H03198355A JP 33969889 A JP33969889 A JP 33969889A JP 33969889 A JP33969889 A JP 33969889A JP H03198355 A JPH03198355 A JP H03198355A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- lead
- semiconductor element
- lead frame
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000011347 resin Substances 0.000 claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 abstract description 5
- 238000007789 sealing Methods 0.000 abstract description 3
- 239000004593 Epoxy Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 238000005219 brazing Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に電気特性が高速化した
半導体装置や、多ピン化により外径寸法が大きくさらに
インナーリード部が微細化した半導体装置に関するもの
である。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor devices, and in particular to semiconductor devices with faster electrical characteristics, and semiconductors with larger outer diameters due to increased pin count and smaller inner leads. It is related to the device.
従来の樹脂封止形半導体装置の製造方法は、第２図及び
第３図のように、外部端子２１．アイランド部２ｊ、イ
ンナーリード部２ｋを有するリードフレーム２ｎ上のア
イランド部２ｊに半導体素子３ｃをロー材３ｂにより固
定載置され、次に２５〜３０μφのＡｕまたはＡｕ２の
極細線（ワイヤー）で半導体素子上のＡｉ７電極とリー
ドフレーム上のインナーリードとを一本づつ順次接続す
る。In the conventional method of manufacturing a resin-sealed semiconductor device, as shown in FIGS. 2 and 3, external terminals 21. A semiconductor element 3c is fixedly mounted on an island part 2j on a lead frame 2n having an island part 2j and an inner lead part 2k with a brazing material 3b, and then the semiconductor element is fixed with a 25 to 30 μΦ Au or Au2 ultrafine wire. Connect the upper Ai7 electrodes and the inner leads on the lead frame one by one.
さらに、取扱いやすく、又機械的保護の為、外部端子２
１を残し第３図のように樹脂３に封止を行う、最後に接
続されていた外部端子２１を切り離し、所望の形状に外
部端子の整形を行うことにより実施していた。Furthermore, for ease of handling and mechanical protection, external terminal 2
This was accomplished by sealing all but 1 in the resin 3 as shown in FIG. 3, cutting off the last connected external terminal 21, and shaping the external terminal into the desired shape.
上述した従来の半導体装置では、半導体素子上の電極端
子が増大するに従い、外部端子の数もこれに従って一定
間隔で増大するため半導体装置の外径寸法も増大する。In the conventional semiconductor device described above, as the number of electrode terminals on the semiconductor element increases, the number of external terminals also increases at regular intervals, and therefore the outer diameter of the semiconductor device also increases.
Ｇ／Ａ等では機能数の増大とともに、電極端子数も現状
約５００端子程度にまで著じるしく増大しており、前述
した如く半導体装置の大きさは、わずかに数１０−の半
導体素子を取扱うのに数１０ＣＪＡと大きくなっている
。さらに、多ピン化にともないリードフレームのインナ
ーリード２ｋが長く微細化していく。従ってリードフレ
ーム作成及びワイヤーポンディングが困難であり歩留り
の低下をきたしてしまう。又、組立工程中のトラブルに
よりインナーリードが変形することが多く、組立歩留り
低下の原因ともなっていた。With the increase in the number of functions in G/A, etc., the number of electrode terminals has also increased significantly, to about 500 terminals at present, and as mentioned above, the size of semiconductor devices is only a few dozen semiconductor elements. It is large, several tens of CJA, to handle. Furthermore, as the number of pins increases, the inner leads 2k of the lead frame become longer and finer. Therefore, lead frame creation and wire bonding are difficult, resulting in a decrease in yield. Furthermore, the inner leads are often deformed due to trouble during the assembly process, which also causes a decrease in assembly yield.
最近の電子機器では、前述した多ビン化のみならず高速
化も要求されており、高速ディジタルシステムのクロッ
クは１００ＭＨｚ以上にもなり、これに使用される半導
体素子の立ち上り時間が１ｎＳ以下となっている。この
ような半導体素子の内部配線には形状により寄生のイン
ダクタンスやキャパシタンス抵抗が存在し、特性インピ
ーダンスや伝搬遅延といった伝送線路の特性を持ち、電
気特性に大きな影響を与えている。つまり、半導体装置
内のインナーリードについて半導体素子と特性インピー
ダンスのマツチングが取られなければ、信号の反射が生
じ、外部端子での信号波形にひずみが生じる。しかしな
がら、従来の半導体装置においては構造上、半導体素子
とインピーダンスマツチングを取ることが困難であると
いう欠点を有している。In recent electronic devices, not only the number of bins mentioned above but also higher speeds are required.The clock speed of high-speed digital systems has increased to 100MHz or more, and the rise time of the semiconductor elements used in this has become less than 1ns. There is. The internal wiring of such a semiconductor element has parasitic inductance, capacitance, and resistance depending on its shape, and has transmission line characteristics such as characteristic impedance and propagation delay, which greatly influences electrical characteristics. In other words, if the characteristic impedance of the inner lead in the semiconductor device is not matched to that of the semiconductor element, signal reflection will occur and the signal waveform at the external terminal will be distorted. However, conventional semiconductor devices have a disadvantage in that it is difficult to achieve impedance matching with semiconductor elements due to their structure.
上述した従来の半導体装置に対し、本発明は多層配線パ
ターンを有した基板部材に半導体素子を固定載置ポンデ
ィングし、その後その基板部材をリードフレームにポン
ディングするという相違点を有している。The present invention differs from the conventional semiconductor device described above in that a semiconductor element is fixedly placed and bonded on a substrate member having a multilayer wiring pattern, and then the substrate member is bonded to a lead frame. .
本発明の半導体装置は半導体素子が固定されるアイラン
ド部と、前記アイランド部の周縁に位置したインナーリ
ードボンディングパッドと外周部に位置したアウターリ
ードボンディングパッドと２層以上の配線パターンとを
少なくとも有した基板部材があって、前記基板部材のア
イランド部に半導体素子が固定載置さｈ、半導体素子の
電極と基板のインナーリードボンディングパッド及び基
板のアウターリードボンディングパッドと外部端子とが
各々ワイヤー又はリードにより接続され、かつ外部端子
の一部を残して基板部材、半導体素子、外部端子の一部
等が樹脂封止されている構造を少なくとも有している。The semiconductor device of the present invention has at least an island portion to which a semiconductor element is fixed, an inner lead bonding pad located on the periphery of the island portion, an outer lead bonding pad located on the outer periphery, and a wiring pattern of two or more layers. There is a substrate member, a semiconductor element is fixedly mounted on an island portion of the substrate member, and an electrode of the semiconductor element and an inner lead bonding pad of the substrate, and an outer lead bonding pad of the substrate and an external terminal are connected by wires or leads, respectively. It has at least a structure in which the substrate member, the semiconductor element, a part of the external terminal, etc. are connected with resin and are sealed with resin except for a part of the external terminal.
以下、本発明による半導体装置を詳細に説明する。 Hereinafter, a semiconductor device according to the present invention will be explained in detail.
第１図（断面図）は、本発明の一実施例である。FIG. 1 (cross-sectional view) shows one embodiment of the present invention.
半導体装置中央部にガラスエポキシ等を用いた多層配線
板ａが位置しており、この基板ａ中央部の凹構造を持っ
たアイランド部には、半導体素子ＩＣがロー材１ｂによ
り固定載置されている。半導体素子１ｃは２５〜３０μ
φのワイヤー１８により基板のインナーリードボンディ
ングパッド部ｄに接続され、外部端子１１はアウターリ
ード１ｈによりリードフレームの外部端子１１と接続さ
れている。又、半導体装置は外部端子１１を残し機械的
保護の為樹脂１ｈにより封止されている。A multilayer wiring board a made of glass epoxy or the like is located in the center of the semiconductor device, and a semiconductor element IC is fixedly placed on an island portion having a concave structure in the center of the board a with a brazing material 1b. There is. Semiconductor element 1c has a thickness of 25 to 30μ
It is connected to the inner lead bonding pad portion d of the substrate by a wire 18 of φ, and the external terminal 11 is connected to the external terminal 11 of the lead frame by an outer lead 1h. Further, the semiconductor device is sealed with resin 1h for mechanical protection except for external terminals 11.
以上の構成において本発明の半導体装置の製造方法につ
いて記述する。先ず、半導体素子１ｃと所望の多層配線
パターンを設けた基板ａを準備し、ロー材を用いて半導
体素子をアイランド部１ｊに固定載置する。次に半導体
素子と基板をワイヤ・・−により一本づつ接続する。こ
こでワイヤーの代わりにＴＡＢ方式によるリードポンデ
ィングも可能である。その後、外部端子部１１となるリ
ードフレームを準備し、アウターリードｇにより接続す
る。このアウターリードは基板ａにあらかじめ設けたも
のを用いる。最後に、樹脂封止後外部端子を切り離し整
形を行う。A method for manufacturing a semiconductor device according to the present invention will be described with the above configuration. First, a substrate a on which a semiconductor element 1c and a desired multilayer wiring pattern are provided is prepared, and the semiconductor element is fixedly placed on the island portion 1j using a brazing material. Next, the semiconductor elements and the substrate are connected one by one using wires. Here, lead bonding using the TAB method is also possible instead of using wires. Thereafter, a lead frame that will become the external terminal section 11 is prepared and connected using the outer lead g. These outer leads are those provided in advance on the substrate a. Finally, after resin sealing, the external terminals are separated and shaped.
本実施例で用いられる基板ａは誘電体にガラスエポキシ
を用いた２〜６層の多層構造を持ち、信号配線層の上下
層もしくは片側層には接地面（ＧＮＤ。The substrate a used in this example has a multilayer structure of 2 to 6 layers using glass epoxy as a dielectric, and has a ground plane (GND) on the upper and lower layers or on one side of the signal wiring layer.
パターン）が設けられストリップ線路もしくはマイクロ
ストリップ線路構造が取られている。これにより、半導
体素子とマツチングの取れた特性インピーダンス（ＥＣ
Ｌでは５０Ω、０ＭＯ８では４００Ω程度等）を持つよ
うに配線パターンを設計することが容易となる。しかし
ながら、本実施例においては、ワイヤー１ｅ、アウター
リードｇ、外部端子１１でのインピーダンスマツチング
は困難でありできるだけ短くするのが望ましい。A strip line or microstrip line structure is provided. As a result, the characteristic impedance (EC
It is easy to design the wiring pattern so that the resistance is 50Ω for L, about 400Ω for 0MO8, etc.). However, in this embodiment, impedance matching between the wire 1e, the outer lead g, and the external terminal 11 is difficult, and it is desirable to make them as short as possible.
以上、説明した本発明の半導体装置においては、高速化
された素子を取り扱う場合においても内部配線の多くの
部分を素子の特性インピーダンスに合わせることが可能
である為、内部配線での信号の反射を軽減し、波形のひ
ずみを低く押えることが可能である。又、多ピン化され
た半導体装置においては、図２のようにインナーリード
２ｋが微細化、長大化し変形しやすくなっていた。しか
しながら本発明においては、リードフレームのリード部
を短くかつ太くすることができ組立歩留りの向上を図る
ことができる。尚、上記実施例ではアウターリードｇを
基板ａに設けてリードフレームの外部端子１１との接続
を行なったが、リードではなく基板外周にパッドとして
アウターリードパッドを設け、ワイヤーにより外部端子
１１との接続を実施しても良い。このとき基板ａの載置
用としてリードフレームに基板載置固定用のアイランド
を設けておくことが必要となる。As described above, in the semiconductor device of the present invention described above, even when handling high-speed elements, it is possible to match many parts of the internal wiring to the characteristic impedance of the element, so it is possible to prevent signal reflection in the internal wiring. It is possible to suppress waveform distortion to a low level. Furthermore, in a semiconductor device with a large number of pins, the inner lead 2k becomes finer, longer, and more easily deformed, as shown in FIG. However, in the present invention, the lead portion of the lead frame can be made shorter and thicker, and the assembly yield can be improved. In the above embodiment, the outer lead g was provided on the board a to connect to the external terminal 11 of the lead frame. You may also perform a connection. At this time, it is necessary to provide an island on the lead frame for mounting and fixing the substrate a.
以下に本発明の他の実施例について説明する。Other embodiments of the present invention will be described below.
第１図の実施例においては、ガラスエポキシ基板を使用
していた多層基板ａに、本実施例ではＣｕポリイミド基
板を使用する。Ｃｕポリイミド基板は通常以下のように
作成される。In the embodiment shown in FIG. 1, a glass epoxy substrate was used as the multilayer substrate a, but in this embodiment, a Cu polyimide substrate is used. A Cu polyimide substrate is usually produced as follows.
（１）セラミック基板上に電源や接地などの粗い配線を
作っておき、その上にポリイミドの前駆体を塗って加熱
し、１０〜２０μｍ程度の絶縁層を作る。(1) Rough wiring for power supply, grounding, etc. is made on a ceramic substrate, and then a polyimide precursor is applied and heated to form an insulating layer with a thickness of about 10 to 20 μm.
（２）前記絶縁層にフォトレジストを塗布し、露光、現
象、エツチング工程を経て、ピアホールを作る。(2) Coat a photoresist on the insulating layer, and create a peer hole through exposure, development, and etching steps.
（３）次に蒸着スパッタリングなどで膜厚５〜１０μｍ
、幅１０〜５０μｍのＣｕ配線層を作る。(3) Next, film thickness is 5 to 10 μm by vapor deposition sputtering etc.
, a Cu wiring layer with a width of 10 to 50 μm is made.
（４）配線層の上にポリイミドの絶縁層を作る。(4) Create a polyimide insulating layer on the wiring layer.
（５）以上（２）〜（４）をくり返し、多層配線基板を
作る。(5) Repeat steps (2) to (4) above to produce a multilayer wiring board.
このようなＣｕポリイミド基板は、一般にガラスエポキ
シ基板等に比べ非常に高価であるが、次のような利点を
持っている。Although such a Cu polyimide substrate is generally much more expensive than a glass epoxy substrate or the like, it has the following advantages.
（１）誘電率が３〜３．５（ガラスエポキシ約４．７゜
セラミック約１０）と低い為、信号の伝搬遅延時間を短
縮することができる。(1) Since the dielectric constant is as low as 3 to 3.5 (approximately 4.7 degrees for glass epoxy and approximately 10 degrees for ceramics), signal propagation delay time can be shortened.
（２）厚い絶縁膜が容易に作れる為、配線容量を小さく
できる。(2) Since a thick insulating film can be easily made, the wiring capacitance can be reduced.
（３）フォトリングラフィ技術を使う為、微細加工の制
約がない。(3) Since photolithography technology is used, there are no restrictions on microfabrication.
従って第１図の実施例に比べ、より多ビン化。Therefore, compared to the embodiment shown in FIG. 1, the number of bins is higher.
高速化し、さらに、外部端子ピッチが狭くなった場合に
有効である。This is effective when the speed is increased and the external terminal pitch is narrowed.
以上説明したように本発明は、多ピン化により微細化、
長大化した半導体装置のインナーリ・−ド部を多層配線
基板により構成したものである。これにより、半導体装
置の内部配線の多くの部分を素子の特性インピーダンス
に合わせることが容易となり、内部配線部分での信号波
形のひずみを低減することができる。又、多ピン化によ
り微細化、長大化したリードフレームのインナーリード
部を短くすることができる為、インナーリード変形によ
る組立歩留り低下を未然に防止することができるという
効果がある。特に、多ピン化、高速化した半導体装置に
おいて、この効果が著しい。As explained above, the present invention achieves miniaturization by increasing the number of pins.
The inner lead portion of an elongated semiconductor device is constructed from a multilayer wiring board. This makes it easy to match many parts of the internal wiring of the semiconductor device to the characteristic impedance of the element, and it is possible to reduce distortion of signal waveforms in the internal wiring parts. Furthermore, since the inner lead portion of the lead frame, which has become finer and longer due to the increased number of pins, can be shortened, it is possible to prevent a decrease in assembly yield due to inner lead deformation. This effect is particularly remarkable in semiconductor devices with increased pin count and increased speed.
第１図に本発明の実施例を示す断面図である。
第２図、第３図は従来の半導体装置を示し、第２図はリ
ードフレームの平面図、第３図はリードフレームに半導
体素子を実装し組立てた後の断面図である。
符号の説明
ａ・・・・・・多層配線基板、ｌｂ、３ｂ・・・・・・
ロー材、ｌｃ、３ｃ・・・・・・半導体素子、ｄ・・・
・・・インナーリードボンディングパッド、ｌｅ、３ｅ
・・・・・・ワイヤーｆ・・・・・・アウターリードボ
ンディングパッド、ｇ・・・・・・アウターリード、ｌ
ｈ、３ｈ・・・・・・封入樹脂、１１゜２ｉ、３ｉ・・
・・・・外部端子、ｌｊ、２ｊ、３ｊアイランド部、２
ｋ・・・・・・インナーリード、２１・・・・・・つり
ビン、２ｍ・・・・・・タイバー ２ｎ・・・・・・リ
ードフレーム。FIG. 1 is a sectional view showing an embodiment of the present invention. 2 and 3 show a conventional semiconductor device, FIG. 2 is a plan view of a lead frame, and FIG. 3 is a sectional view after a semiconductor element is mounted on the lead frame and assembled. Explanation of symbols a...Multilayer wiring board, lb, 3b...
Low material, lc, 3c...semiconductor element, d...
...Inner lead bonding pad, le, 3e
...Wire f...Outer lead bonding pad, g...Outer lead, l
h, 3h... Encapsulation resin, 11゜2i, 3i...
...External terminal, lj, 2j, 3j island part, 2
k...Inner lead, 21...Hanging bottle, 2m...Tie bar 2n...Lead frame.
Claims (1)
ド部の周縁に位置したインナーリードボンディングパッ
ドと外周部に位置したアウターリードボンディングパッ
ドと２層以上の配線パターンとを少なくとも有した基板
部材を有し、前記基板部材のアイランド部に半導体素子
が固定載置され、半導体素子の電極と基板のインナーリ
ードボンディングパッド及び基板のアウターリードボン
ディングパッドと外部端子とが各々ワイヤー又はリード
により接続され、かつ外部端子の一部を残して基板部材
、半導体素子、外部端子の一部等が樹脂封止されている
構造を有することを特徴とする半導体装置。A substrate member having at least an island portion to which a semiconductor element is fixed, an inner lead bonding pad located at the periphery of the island portion, an outer lead bonding pad located at the outer periphery, and two or more layers of wiring patterns, A semiconductor element is fixedly placed on the island portion of the substrate member, and the electrodes of the semiconductor element and the inner lead bonding pads of the substrate and the outer lead bonding pads of the substrate and external terminals are respectively connected by wires or leads, and 1. A semiconductor device having a structure in which a substrate member, a semiconductor element, a part of an external terminal, etc. are sealed with resin except for a part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1339698A JP2789750B2 (en) | 1989-12-26 | 1989-12-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1339698A JP2789750B2 (en) | 1989-12-26 | 1989-12-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03198355A true JPH03198355A (en) | 1991-08-29 |
| JP2789750B2 JP2789750B2 (en) | 1998-08-20 |
Family
ID=18329954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1339698A Expired - Lifetime JP2789750B2 (en) | 1989-12-26 | 1989-12-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2789750B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6292653U (en) * | 1985-11-29 | 1987-06-13 | ||
| JPH0277145A (en) * | 1988-09-13 | 1990-03-16 | Ibiden Co Ltd | Semiconductor device |
-
1989
- 1989-12-26 JP JP1339698A patent/JP2789750B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6292653U (en) * | 1985-11-29 | 1987-06-13 | ||
| JPH0277145A (en) * | 1988-09-13 | 1990-03-16 | Ibiden Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2789750B2 (en) | 1998-08-20 |
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