JPS6292618A - Deglitch circuit - Google Patents

Abstract

PURPOSE:To reduce the adverse effect onto a reproducing analog signal by connecting the 2nd switching means in parallel with the 1st switching means and making a control input of the 2nd switching means as an inverted signal to the control input of the 1st switching means. CONSTITUTION:A control signal C via an inverter 23 is applied to analog switches 21, 22 as a control input. Since the control signal and its inverting signal are fed respectively to the control input terminal of analog switches 9, 21 in the deglitch circuit 20, crosstalk noise of opposite polarity is generated in each output of the analog switches 9 and 21 and canceled together. Similarly, since the control signal C and its inverted signal are fed respectively to the control input terminal of the analog switches 10, 22, the outputs of the analog switches 10, 22 have crosstalk noises of opposite polarity and they are canceled together.

Description

Detailed Description of the Invention L11 The present invention relates to a diglitch circuit, and in particular to a diglitch circuit that removes so-called glitches that occur in the output of a digital-to-analog converter (hereinafter abbreviated as a D/A converter). In some cases, a spike-like distortion waveform called a glitch may occur before the output stabilizes.

This is due to variations in turn-on and turn-off times of transistors inside the D/A converter.

The conventional deglitch circuit that removes this glitch is
As shown in the figure. In FIG. 3, L and R channel digital data obtained by sampling the L and R channel analog signals at every predetermined FT interval are supplied to a current integrating type D/A converter 1. In addition, °these L
It is assumed that the sampling times of each channel of the digital data of the R channel and the R channel are shifted from each other by a time corresponding to about 1/2 of the sampling period. The D/A converter 1 has levels corresponding to the digital data of the left and right channels, respectively, and outputs the quantized signals of the right channel and the quantized signals of the left and right channels at the same time. The control signal C is configured to output a control signal C whose state changes when the signals dl and d2 indicating whether the quantization signals of the L and R channels are stabilized. The L and R channel quantized signals output from the D/A converter 1 are supplied to negative input terminals of operational amplifiers 2 and 3, respectively. Operational amplifiers 2 and 3
The positive input terminal of is grounded. Operational amplifiers 2 and 3
A capacitor C is connected between the negative input terminal and output terminal of
1 and C2 and FETCl field effect transistor) 4
and 5 are connected in parallel. FET4 and 5
Signals d, , d2 are supplied to each gate of .

At the same time, a power source -Vcc is applied to each gate of FETs 4 and 5 via resistors R1 and R2, respectively. Each of these operational amplifiers 2 and 3 has a capacitor C+
, Cz and each of FET4.5.
Each voltage conversion circuit 6.7 is formed.

Each output of the current/voltage conversion circuit 6.7 is supplied to a diglitch circuit 8. In the diglitch circuit 8, each output of the current/voltage conversion circuit 6.7 is connected to a resistor R3, R
4 and analog switches 9 and 10 to the negative input terminals of operational amplifiers 11 and 12, respectively.

The analog switch 9.10 has a movable contact a and a fixed contact bl.

b2, and has a function of acting as a changeover switch in which the movable contact a contacts one of the fixed contacts b1 and b2 depending on the level of the control input. however,
The analog switch 9 is connected to act as an open/close switch that is turned on when the control input is at a high level, and the analog switch 10 is connected to act as an open switch that is turned on when the control input is at a low level. There is.

Each positive input terminal of operational amplifiers 11 and 12 is grounded. Capacitors C3 and C4 are connected between each negative input terminal and each output terminal of the operational amplifiers 11 and 12, respectively. Resistors R5 and R6 are connected between each input terminal of analog switches 9 and 10 and each output terminal of operational amplifiers 11 and 12, respectively. In addition, analog switch 9,
A power source -Vcc is applied to each input terminal of the circuit 10 via resistors R7 and Rs, respectively.

Each output of the operational amplifiers 11 and 12 is connected to the diglitch circuit 8.
It is outputted as an output through each of low-pass filters 13 and 14.

In the above configuration, signals d1 and d2 as shown in FIG. 4(A) and FIG. 4(G) are output, and the signal d1
When d2 is at a high level, one of the quantized signals of the L and R channels is output from the D/A converter 1 and supplied to the current/voltage conversion circuit 6, and when the signal d2 is at a low level, the quantized signals of the L and R channels are It is assumed that the other of the quantized signals is output from the D/A converter 1 and supplied to the current/voltage conversion circuit 7. At this time, the current/voltage conversion circuits 6 and 7
i! of the quantized signal from the D/A converter 1 at The current level is converted to a voltage level, and voltage signals as shown in FIGS. 4(B) and 4(F) are outputted from the current/voltage conversion circuits 6 and 7, respectively.

On the other hand, in the diglitch circuit 8, when the analog switch 9 is on, the output of the current/voltage conversion circuit 6 is amplified with a gain determined by the resistors R3, Rs, and R7, and is led out to the output terminal of the operational amplifier 11. Then, when the analog switch 9 is turned off, the output of the operational amplifier 11 is held constant at the level immediately before the analog switch y-9 was turned off.

Similarly, when the analog switch 10 is on, the resistance Ra
, R6, and Re, the output of the current/voltage conversion circuit 7 is amplified and delivered to the output terminal of the operational amplifier 12. Then, when the analog switch 1o is turned off, the output of the operational amplifier 11 is held constant at the level immediately before the analog switch 10 is turned off.

Therefore, as shown in FIG. 4(D), the control signal C remains at a high level after the level of the quantized signal of the L channel becomes stable until it temporarily disappears, and the quantized signal of the R''f-channel remains high. If the level of the signal stabilizes and then becomes low until it temporarily disappears, the stable level of the L and R channel quantized signals will be maintained, as shown in Figure 4 (C).
) and (E), the glitch has been removed and the quantized signal of the R channel is led out to the output terminals of the operational amplifiers 11 and 12 and becomes the output of the deglitch circuit 8. The signals output from this diglitch circuit 8 and R
The quantized signal of the channel is passed through the low-pass filters 13 and 1.
4 to obtain a signal equivalent to the original and R channel analog signals.

The control signal C is mixed into the outputs of the analog switches 9 and 10 in the conventional diglitch circuit 8 as described above due to crosstalk.

FIGS. 5 and 6 are diagrams showing how a control signal is mixed into the output of an analog switch. In FIG. 5, a resistor R+e is connected between one input/output terminal lN10UT of the analog switch 17 and the ground. A capacitor C5 and a resistor Rn are connected as a load between the other input/output terminal OUT/IN of the analog switch 17 and ground.

One of the four IIJII input terminals of the analog switch 17 is supplied with a pulse as shown in FIG. 6(A) from the pulse generator 18. At this time, one input/output terminal lN10UT of the analog switch 17 is grounded via the resistor R+a, so the other input/output terminal OUT/
No signal should appear at IN, but as shown in FIG. 6 (8), positive polarity pulses are generated from the other input/output terminal OUT/IN at the rise and fall of the output pulse of the pulse generator 18, respectively. and negative polarity pulses are generated as crosstalk noise.

Therefore, the conventional diglitch circuit 8 has a drawback in that the quality of the reproduced sound from the reproduced analog signal deteriorates due to the crosstalk noise generated in the outputs of the analog switches 9 and 10.

1L An object of the present invention is to provide a diglitch circuit that suppresses crosstalk noise of analog switches and does not adversely affect reproduced analog signals.

In the diglitch circuit according to the present invention, the control input is the first logic J
! When removing glitches by turning on and off the first switching means that is turned on when the IIJI11 input is in a state corresponding to the second logic value, the second switching means is turned on and off when the IIJI11 input is in a state corresponding to the second logical value
The second switching means is connected in parallel with the switching means, and the control input of the second switching means is a signal having the opposite phase of the control input of the first switching means.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 and 2. As shown in FIG. 1, a diglitch circuit 20 according to the present invention
In analog switch 9.10. Operational amplifier 11.
12. Resistors R3 to R8 and capacitors C3 and C4 are connected in the same way as the circuit shown in FIG. However, in this example, rMrA turns on when the control input is at a low level.
An analog switch 21 connected to act as a switch is provided in parallel to the analog switch 9.

Also, an analog switch 2 connected to act as an open/close switch that turns on when the control input is at a high level.
2 are provided in parallel to the analog switch 10. An inverter 23 is connected to these analog switches 21 and 22.
The lIiIJm signal C that has passed through is supplied as the IIJwJ input.

In the above configuration, similar to the circuit shown in FIG. 3, the D/A converter 1 sends signals d as shown in FIGS.
When I, d2 are output and these signals d+, dz are at high level, the L and R channels are quantized (if the fi signal is output from the D/A converter B1, the current/voltage converters rR6 and Voltage signals as shown in FIG. 7 (B) and FIG. 7 (G) are output as quantized signals of L and R channels.

On the other hand, in the diglitch circuit 20, when one of the analog switches 9 and 21 is on, the resistors R3 and Rs
, Ry, the output of the current/voltage conversion circuit 6 is amplified and delivered to the output terminal of the arithmetic layer 11. Then, when both analog switches 9 and 21 are turned off, the output of the 8I calculation amplifier 11 is transferred to the analog switch 9.
It is held constant at the level immediately before turning off of 21. Similarly, when one of the analog switches 10 and 22 is on, the output of the current/voltage conversion circuit 7 is amplified with a gain determined by the resistors R4, R6, and R11, and is led to the output terminal of the operational amplifier 12. When analog switches 10 and 22 are both turned off, the output of operational amplifier 12 is held constant at the level when analog switches 10 and 22 are turned off.

Therefore, as shown in FIG. 2(C), the control signal C remains at a high level after the level of the L channel quantized signal stabilizes until the same signal temporarily disappears, and the level of the R channel quantized signal remains high. When the signal becomes low level until it temporarily disappears after stabilizing, the control inputs of the analog switches 21 and 22 become signals with the opposite phase of the control signal C, as shown in FIG. 2(E). The stable levels of the L and R channel quantized signals are continuously output from the operational amplifiers 11 and 12, respectively. As a result, Figure 2 (C)
As shown in FIG. 2 and (), the glitch that occurs from the time when the output of the quantized signal starts until the level stabilizes is removed, and the quantized signal of the R channel is output from the operational amplifiers 11 and 12. Diglitch circuit 2o
The output is The output of this degree circuit 20 is the third
Similar to the circuit shown in the figure, the signals are smoothed by low-pass filters 13 and 14 to reproduce signals equivalent to the original L and R channel analog signals.

In the diglitch circuit 20 according to the present invention as described above, the control signal C and the reverse phase signal of the control signal C are supplied to the control input terminals of the analog switches 9 and 21, respectively, so that the outputs of the analog switches 9 and 21 are Crosstalk noises of opposite polarity occur and cancel each other out. Similarly, analog switches 10 and 2
Since the υ control signal C and the opposite phase signal of the control signal C are supplied to the control input terminals of the analog switches 10 and 22, crosstalk noises of opposite polarity occur at the outputs of the analog switches 10 and 22, and cancel each other out. It will match. Therefore, the adverse effect on the reproduced analog signal due to the crosstalk noise of the analog switch is reduced.

In the above embodiment, a case has been described in which glitches are removed from the output of a current integrating type D/A converter having output terminals for two channels, but a resistive ladder type D/A converter having output terminals for one channel is The present invention can be applied even when removing glitches from the output of the A converter.

As described in detail above, the diglitch circuit according to the present invention is capable of removing glitches by turning on and off the first switching means, which is turned on when the control input is in a state corresponding to the first logical value. A second switching means that turns on a state corresponding to two logical values is connected in parallel to the first switching means, and the control input of the second switching means is a reverse phase signal of the control input of the first switching means. As a result, cross-down signals of opposite polarity occur in the outputs of the first and second switching means and cancel each other out, making it possible to reduce the adverse effects on the reproduced analog signal.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of each part of the circuit in FIG. 1, and FIG.
The figure is a circuit block diagram showing a conventional diglitch circuit.
Figure 4 is a waveform diagram showing the operation of each part of the circuit in Figure 3. Figure 5 is a block diagram showing a method for measuring crosstalk noise of an analog switch. FIG. Invention of codes of main parts 9.10, 21.22...Analog switch 2
3...Inverter

Claims (1)

[Claims] The first switching means includes a first switching means that is turned on when the control input is in a state corresponding to a first logical value, and generates and outputs a signal according to the input signal when the first switching means is on, and the first switching means a deglitch circuit whose output is constant at an instantaneous level immediately before the first switching means is turned off when the circuit is off, the circuit being connected in parallel to the first switching means and having a control input corresponding to a second logical value; 1. A diglitch circuit comprising: a second switching means that is turned on when the first switching means is in a state in which the deglitch circuit is turned on, and a control input of the second switching means is a signal having an opposite phase to a control input of the first switching means.