JP3885911B2 - D / A converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a D / A converter that converts a digital signal into an analog signal, and in particular, a delta-sigma D / D that can improve the S / N ratio (ratio of full-scale signal output to residual noise at no signal). It relates to the A converter.
[0002]
[Prior art]
Since the delta-sigma D / A converter has high resolution and good linearity, it has been actively applied to audio equipment and video equipment in recent years.
[0003]
For example, when a 16-bit PCM signal having a certain sampling rate is given, the delta-sigma D / A converter converts the PCM signal into a PCM signal having a higher sampling rate, and then a 1-bit bit stream signal by a digital sigma modulator. Are converted into analog reference potentials + V and −V corresponding to the bit stream signal, and converted into an analog signal through a low-pass filter circuit.
[0004]
By performing delta-sigma modulation, the quantization noise generated at the time of PCM signal conversion is shifted to a high frequency, and the noise in a low frequency region is reduced. This is called noise shaping, and it is possible to greatly improve the S / N ratio of the voice band existing in the low frequency region by this noise shaping.
[0005]
In addition, the delta-sigma D / A converter performs D / A conversion on the PCM signal after noise shaping. However, since the analog signal has quantization noise shifted to a high frequency, for example, a switched capacitor filter ( Noise outside the voice band is removed through a low-pass filter circuit such as SCF).
[0006]
In addition, in the D / A converter, there is a demand to increase the S / N ratio, and in order to realize this, a part of the circuit system is electrically connected so that no leakage of system clock or noise is output during silence. It has been proposed to disconnect the output path and to mute the signal.
[0007]
[Problems to be solved by the invention]
However, the disconnection of the output path has a problem that it is difficult to maintain the voltage of the path at the time of disconnection or connection, and noise is generated.
[0008]
In the case of a normal D / A converter such as a weighted current source type, if the PCM digital signal is constant, there is no switching and no switching noise is generated, but in the delta-sigma modulator, the PCM signal is constant. In this case, as a 1-bit signal, signals corresponding to “+1” and “−1” are alternately output around the reference voltage, and there is a problem in that switching noise is large in principle.
[0009]
The present invention has been made to solve such a conventional problem, and an object thereof is to provide a delta-sigma D / A converter capable of improving the S / N ratio.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, an invention according to claim 1 is directed to a delta-sigma modulation circuit that converts multi-bit PCM data into a data stream, a low-pass filter circuit to which the data stream is input, and its own inverting input. A signal filtered by the low-pass filtering circuit is input to at least one of the terminal and the non-inverting input terminal via a first impedance element whose impedance is variable or fixed. , Yes between its input terminal and an output terminal, and a mute circuit and a second impedance element of the MOS transistor and the impedance fixing comprises a connected operational amplifier in parallel to the impedance is changed by the voltage of the gate terminal, the The MOS transistor is in an off state when not muted, and when muted, Pressure is changed slowly, a D / A converter, characterized in that it consists of the OFF state to the ON state.
[0011]
Note that the first impedance element may be variable or fixed, and the second impedance element may be variable, so that the amplification factor of the mute circuit is variable.
The invention according to claim 2 is the invention according to claim 1,
Including a silence detection circuit for detecting that the state in which the PCM data is silent for a predetermined time continues,
The silence detection circuit is configured to reduce the amplification factor of the mute circuit when detecting a state where the PCM data is silent for a predetermined time.
[0012]
Furthermore, the invention according to claim 3 is the invention according to any one of claims 1 and 2,
The amplification factor of the mute circuit is configured to change gradually.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram of a D / A converter according to an embodiment of the present invention. This D / A converter is a digital interpolator that interpolates a signal between sample points when a PCM signal Din is given. A delta-sigma modulator 20 that performs delta-sigma modulation of a digital signal, a 1-bit D / A converter 30 that performs D / A conversion of a 1-bit digital signal, a low-pass filter 40, and a low-pass filter 50 A mute circuit 60 for muting the signal when there is no sound and a silence detection circuit 70 for detecting that the state in which the PCM data is silent for a predetermined time continues. The silence detection circuit 70 is connected to a predetermined part of the mute circuit 60 by the control line 100.
[0014]
The low-pass filter 40 is configured by, for example, a secondary switched capacitor filter (SCF), and the low-pass filter 50 can be realized by, for example, an RC filter (also referred to as a smoothing filter (SMF)) including a resistor and a capacitor. The 1-bit D / A converter 30 preferably outputs a differential analog signal. In this case, the low-pass filters 40 and 50 also operate differentially, and the mute circuit 60 converts the differential input to a single-ended output.
[0015]
FIG. 2 is an example of a configuration diagram of the silence detection circuit 70. The silence detection circuit 70 is based on the silence detection unit 71 that detects that the PCM signal is “0” and the detection result by the silence detection unit 71. A counter 72 that counts the time during which the PCM signal is “0”, and when the count result of the counter 72 is equal to or greater than a predetermined value, it is determined that there is no sound, and a control signal is sent to the mute circuit 60 via the control line 100. And a control unit 73 for supplying
[0016]
FIG. 3 is a circuit diagram of the mute circuit 60. The mute circuit 60 includes an operational amplifier 65 having an output terminal for outputting an audio signal, and each of the inverting input terminal and the non-inverting input terminal of the operational amplifier 65 has a resistance. R1 is connected.
[0017]
A MOS transistor 61 and a resistor R2 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier 65, while between the non-inverting input terminal and the output terminal of the operational amplifier 65. The MOS transistor 62 and the resistor R2 are connected in parallel.
[0018]
Further, the control line 100 is connected to the gate terminals of the MOS transistor 61 and the MOS transistor 62, and one of the MOS transistor 62 and the resistor R2 connected between the non-inverting input terminal and the output terminal of the operational amplifier 65. The side is connected to the analog reference potential AGND.
[0019]
The resistance values of the MOS transistors 61 and 62 vary depending on the voltage at the gate terminal. When the combined resistance of the resistance of the MOS transistor and the resistance R2 is R, the amplification factor of the mute circuit 60 is “R / R1”. . For example, when R1 is 40 (kΩ), R2 is 17 (kΩ), and 0 (V) is input as a control signal from the silence detection circuit 70, the combined resistance R is 17 (kΩ), and the amplification factor Is 0.425, but when 5 (V) is supplied as a control signal from the silence detection circuit 70, the MOS transistors 61 and 62 are turned on, the combined resistance R is 500 (Ω), and the amplification factor is 0.0125.
[0020]
Next, the operation of the circuit will be described with reference to FIGS.
Assuming that a signal of “16 bits, fs (sampling frequency) = 44.1 (KHz)” is input as the PCM signal Din, the digital interpolation filter 10 interpolates the signal between the sample points and obtains “16 bits, 64 fs ( Sampling frequency) = 2.8224 (MHz) ”is output.
[0021]
The digital delta sigma modulator 20 to which this signal is input performs delta sigma modulation of this signal and outputs a signal of “1 bit, 64 fs (sampling frequency) = 2.8224 (MHz)”. The 1-bit D / A converter 30 D / A converts this signal and outputs it.
[0022]
Further, the high frequency portion of this output signal is filtered by the low-pass filters 40 and 50. The filtered signal is input to the mute circuit 60. In normal times, the mute circuit 60 differentially amplifies the input signal with an amplification factor determined by “R / R1” as described above, and outputs it as an analog signal via the output terminal.
[0023]
When the PCM signal is “0”, the silence detector 71 detects that the PCM signal is “0”, and the counter 72 detects that the PCM signal is “0” based on the detection result by the silence detector 71. Is counted. Then, when the count result of the counter 72 is equal to or greater than a predetermined value, the control unit 73 determines that there is no sound and supplies a control signal to the mute circuit 60 via the control line 100.
[0024]
As a result, the MOS transistors 61 and 62 are turned on, and the amplification factor of the mute circuit 60 is reduced. Therefore, the noise generated by the circuit preceding the mute circuit 60 is suppressed to a level that can be ignored. At this time, if the control signal input to the MOS transistors 61 and 62 changes suddenly, it causes noise. Therefore, as shown in FIG. 4, when the gate voltage is changed slowly, the combined resistance R also becomes 10 (msec). The mute circuit itself does not become a source of noise. In FIG. 4, V _TH is a threshold voltage.
[0025]
By configuring as described above, assuming that the noise levels in the low-pass filters 40 and 50 and the mute circuit 60 are N1, N2 and N3, the noise level during sound (normal operation) is “N1 + N2 + N3”. However, according to the embodiment of the present invention, the noise level during silence is N3, which is the noise level of only the mute circuit 60, and the S / N ratio can be improved.
[0026]
Furthermore, according to the embodiment of the present invention, the S / N ratio can be improved by automatically performing muting without generating noise or the like at the time of cutting, which has been a problem with a simple configuration. .
[0027]
It is also possible to use a multi-bit delta sigma modulator. In this case, a multi-bit D / A converter such as 4 bits may be used instead of the 1-bit D / A converter.
[0028]
(Experimental value)
Specific experimental values are exemplified as follows. When the resistance R1 is “40k (Ω)” and the resistance R2 is “17k (Ω)” and a 16-bit, 44.1 (KHz) PCM signal is input, the S / N ratio is 100 (dB) in the past. However, according to the present invention, the S / N ratio was 110 (dB), and the S / N ratio was improved.
[0029]
In the above embodiment, the amplification factor of the mute circuit 60 is changed by controlling the MOS transistor connected in parallel with R2 and changing the combined resistance of R2 and the MOS transistor. The amplification factor of the mute circuit 60 may be changed by changing the combined resistance.
[0030]
【The invention's effect】
As described above, according to the first aspect of the present invention, the delta-sigma modulation circuit converts the multi-bit PCM data into the data stream, the low-pass filter filters the high frequency component of the data stream, and the mute circuit Since the amplification factor is variable, the S / N ratio can be improved with a simple configuration.
[0031]
Further, the invention according to claim 2, in addition to the effect of claim 1, further when the silence detection circuit detects a zero state for a predetermined time of the PCM data, by reducing the gain of the muting circuit Unnecessary noise is not generated and muting can be automatically performed to improve the S / N ratio.
[0032]
Further, according to the invention of claim 3, since the amplification factor of the mute circuit changes gently, there is an effect that generation of unnecessary noise is eliminated.
[Brief description of the drawings]
FIG. 1 is a block diagram of a D / A converter according to an embodiment of the present invention.
FIG. 2 is a configuration diagram of a silence detection circuit.
FIG. 3 is a circuit diagram of a mute circuit.
FIG. 4 is an explanatory diagram of the operation of the mute circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Digital interpolation filter 20 Digital delta-sigma modulator 30 1 bit D / A converter 40 Low pass filter 50 Low pass filter 60 Mute circuit 61 MOS transistor 62 MOS transistor 65 Operational amplifier 70 Silence detection circuit 71 Silence detection part 72 Counter 73 Control Part 100 Control line R1 Resistance R2 Resistance

Claims (3)

A delta-sigma modulation circuit that converts multi-bit PCM data into a data stream;
A low-pass filtering circuit to which the data stream is input;
A signal filtered by the low-pass filtering circuit is input to at least one of its own inverting input terminal and non-inverting input terminal via a first impedance element whose impedance is variable or fixed. And a mute circuit comprising an operational amplifier in which an MOS transistor whose impedance is changed by the voltage of the gate terminal and a second impedance element having a fixed impedance are connected in parallel between its own input terminal and output terminal And having
The D / A converter is characterized in that the MOS transistor is in an off state when not muted, and when muted, the voltage at the gate terminal gradually changes to change from an off state to an on state . The claim 1, further comprising:
Including a silence detection circuit for detecting that the state in which the PCM data is silent for a predetermined time continues,
The silence detection circuit, upon detecting a state in which a predetermined time silent PCM data, D / A converter, characterized by being configured so as to reduce the amplification factor of the muting circuit. In any of claims 1 and 2,
A D / A converter characterized in that the amplification factor of the mute circuit is configured to change gradually.

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