JP2003273740A - D/a conversion device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a D/A converter utilizing modulation capable of reducing noise to be generated due to a limit cycle even when an input digital signal is zero while minimizing an increase in circuit scale. <P>SOLUTION: The D/A conversion device is provided with a Δ/Σ modulator 2 for Δ/Σ modulating digital data of multiple bits, a D/A converter 3 for converting the digital data outputted from the modulator 2 into an analog signal, an input detector 5 for detecting the existence of the inputted multi-bit digital signal, and a low pass filter (LPF) 4 capable of switching cut-off frequency and having gain for filtering a high band part of a signal outputted from the D/A converter 3. The LPF 4 is constituted so as to switch a plurality of gains and the gain of the LPF 4 is switched in accordance with the detection output of the input detector 5. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter for converting a digital signal into an analog signal, and in particular,
The present invention relates to a D / A converter that reduces noise during silence in a D / A converter that uses delta-sigma modulation.

[0002]

2. Description of the Related Art Generally, a delta-sigma type D / A converter converts a multi-bit digital signal into a higher sampling frequency by an interpolation filter and applies delta-sigma modulation to bring quantization noise into a high frequency band. Shift to reduce low frequency noise. The noise shifted to the high band is removed by the analog post filter.
In this analog post filter, noise is shifted to a frequency band sufficiently higher than the required frequency band, so that a low-order filter having a smooth attenuation characteristic can be used. High S due to these processes
It is possible to realize a D / A converter having an / N ratio.

Recently, in digital signal processing circuits such as delta sigma modulators and interpolation filters, IIR (Infinite I
mpulse Response) Filters are often used. This I
The IR filter has an advantage over the FIR (Finite Impulse Response) filter in that the circuit scale for obtaining desired characteristics can be smaller, but on the other hand, when the input signal is zero, the output does not become zero and a certain specific value is obtained. Generates noise with a cycle. This phenomenon is called a limit cycle.

As a measure to prevent the above limit cycle, a method of adding dither signals is generally used. However, the problem that the S / N ratio is lowered by the added dither signals and the maximum amplitude that can be input as a signal is the dither signal. There is a problem that it decreases by the amplitude of.

Further, in Japanese Patent Laid-Open No. 4-115722, the presence or absence of a digital signal as an input of a noise shaver (delta sigma modulation) is detected, and when there is no signal, the dither function is stopped and the data in the noise shaver is detected. There is proposed a D / A conversion device configured to reduce noise by clearing.

Japanese Unexamined Patent Publication No. 11-150477 discloses a digital delta-sigma modulation circuit, a low-pass filter,
A mute circuit including an operational amplifier, a silence detection circuit,
And a D / A conversion device configured to reduce the amplification factor of the mute circuit when a silent state is detected.

[0007]

As described above, various methods have been tried to solve the limit cycle.
Along with the increase in circuit scale, there are still problems such as cost increase and power consumption increase.

In view of these circumstances, the present invention solves the problems of cost increase and power consumption increase by maximally utilizing the existing circuit configuration and minimizing the increase in circuit scale. An object of the present invention is to provide a D / A converter using delta sigma modulation that reduces noise due to limit cycles even when the input digital signal is zero.

[0009]

The present invention is directed to a delta-sigma modulator for delta-sigma modulating multi-bit digital data, and a D / A converter for converting digital data output from the delta-sigma modulator into an analog signal. And the above D
A low-pass filter having a gain for filtering a high-frequency part of the signal output from the A / A converter, and an input detector that detects the presence or absence of an input multi-bit digital signal,
The low-pass filter is configured so that a plurality of gains can be switched, and the gain of the low-pass filter can be switched according to the detection output of the input detector.

A VCVS type low-pass filter may be used as the low-pass filter, and the resistance component for determining the gain may be switched according to the detection output of the input detector. Further, the resistors that determine the gain may be connected in series, one resistor may be configured to be detachable by a switch, and the switch may be configured to control according to the detection output of the input detector.

As the low-pass filter, MF
A B-type low-pass filter may be used, and the resistance component that determines the gain may be switched according to the detection output of the input detector. Further, resistors that determine the gain may be connected in parallel, one resistor may be configured to be detachable by a switch, and the switch may be configured to control according to the detection output of the input detector.

As described above, according to the present invention, by adding a simple input detector and a means for switching the gain to the basic structure of the D / A converter utilizing the delta-sigma modulation, the S in the silent state can be obtained. / N can be improved.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a D / A conversion device according to an embodiment of the present invention.

In this embodiment shown in FIG. 1, a multi-bit digital signal (DIN) is input at a sampling frequency fs of 19.2 KHz. Digital signal (D
IN) is an interpolation filter (interpolation filter)
Is input to the digital filter 1. In this digital filter 1, an input signal of 19.2 KHz sampling is converted to 2.4576 MHz 128 times, and an image signal is removed. The digital signal converted to this high sampling frequency is the delta sigma (Δ
Σ) given to the modulator 2.

The applied digital signal is converted into low bits by the delta sigma modulator 2. Here, a 1-bit bit stream signal is generated by the second-order delta-sigma modulator 2. At this time, the quantization noise is shifted to a high band, and the quantization noise distributed in the signal band is reduced. This 1-bit bit stream signal is converted to 1 bit.
It is given to the (bit) D / A converter 3 and converted into an analog signal by the 1-bit D / A converter 3. The converted analog signal is supplied to the low-pass filter 4, and the low-pass filter 4 removes high-frequency noise. The low-pass filter 4 here can use a low-order filter because the noise to be removed is in a sufficiently high band. Here, a second-order low-pass filter is used. An analog output (AOUT) is output from the low pass filter 4. As will be described later, the low-pass filter 4 in this embodiment is composed of a low-pass filter having a gain using an operational amplifier, and this gain is switchable.

Further, as shown in FIG. 1, in this embodiment, a multi-bit digital signal (DIN) is given to the input detector 5, and this input detector 5 judges whether the input signal is zero or not. To be done. When the input detector 5 detects that the input signal is zero, the input detector 5 outputs a switching signal. The gain of the low-pass filter 4 is switched according to this switching signal.

FIG. 2 shows a basic circuit diagram of a low-pass filter having a gain. FIG. 2 shows a second-order VCVS type (positive feedback type) low-pass filter. The low-pass filter 4 includes an operational amplifier 41 and resistors (R) 42, 43, 4
4, 45 and capacitors (C) 46, 47.
The cutoff frequency of the low-pass filter is determined by the values of the capacitor C1 (46) and the resistor R1 (42) in FIG. 2 and can be expressed by the following equation (1).

Fc = 1 / (2π × C1 × R1) (1)

In order to sufficiently pass the voice band and remove high frequency noise, the cutoff frequency is set to about 2 here.
It was set to 0 KHz. At that time, capacitors C1 and C2 (4
6, 47) is 800 pF, and the resistance R1 (41) is 10 KΩ. In addition, the gain is resistance R3, R4 (44,
45) and can be expressed by the following equation (2).

Gain = (R3 + R4) / R3 (2)

Here, the gain is set to about 40 dB. At that time, the value of the resistor R2 (43) is 200Ω and the value of the resistor R3 (4
The value of 4) is set to 20 KΩ.

Low-pass filter 4 according to this embodiment
Is the secondary VCVS type (positive feedback type) shown in FIG.
In the low pass filter, the gain is switched based on the switching signal from the input detector 5. FIG. 3 illustrates a configuration example of the low pass filter 4 according to this embodiment. Basically, the configuration is the same as that of the low-pass filter 4 shown in FIG. 2, but the resistors R3 (44) and R4 (45) are used.
An analog switch 48 is provided between and. The analog switch 48 is turned on / off according to the switching signal from the input detector 5. When the input signal is not zero, the analog switch 48 is on (ON), and the gain of the low pass filter 4 is about 40 dB. When the input signal is zero, the analog switch 48 is turned off (OFF), and the gain of the low pass filter 4 drops to 0 dB.

As described above, when a multi-bit digital signal (DIN) is given to the input detector 5 and the input detector 5 detects that the input signal is zero, the input detector 5 is switched. Output a signal. By lowering the gain of the low-pass filter 4 by about 40 dB in accordance with this switching signal, the signal in the voice band is attenuated and the noise generated by the limit cycle can be reduced. That is, when the input signal is zero, the analog switch 48
Is turned off, and the gain of the low-pass filter 4 is reduced to 0 dB. If the input signal is not zero,
The analog switch 48 is turned on (ON), and the gain of the low-pass filter 4 is about 40 dB.

Therefore, the gain of the low-pass filter 4 is reduced by about 40 dB when there is no sound (when the input signal is zero) as compared with the normal time (when the input signal is not zero).
The signal in the voice band is attenuated by 40 dB, and the noise generated by the limit cycle is also attenuated by 40 dB.

FIG. 4 shows another circuit diagram of the low-pass filter having a gain. FIG. 4 shows a second-order MFB type (multiple negative feedback type) low-pass filter. This low pass filter 4
Is an operational amplifier, resistors R1 and R2 and a capacitor C1,
It is composed of a negative feedback resistor R3 and a capacitor C2. The cutoff frequency of the low-pass filter is the capacitor C in FIG.
1 and the value of the resistor R1, and the gain can be expressed by the following equation (3).

Gain = -R3 / R1 (3)

In the configuration of the low-pass filter shown in FIG. 4, in order to change the gain and reduce the gain, R3
The resistance value of should be reduced. FIG. 5 shows the configuration of an MFB type (multiple negative feedback type) low pass filter in which the gain of the low pass filter 4 is changed according to the switching signal from the input detector 5.

As shown in FIG. 5, a resistor R3 'is provided in parallel with the resistor R3 on the non-feedback side, and the resistor R3 is turned on / off by the analog switch 48. The resistor R3 ′ has a resistance value extremely smaller than that of the resistor R3. When the input signal is not zero, the analog switch 48 is turned on (ON), and the gain of the low pass filter 4 becomes a predetermined gain. When the input signal is zero, the analog switch 48 is turned off (OFF), the resistor R3 is disconnected, and the gain of the low pass filter 4 is reduced to almost 0 dB.

The resistance value of each resistor and the capacitance of the capacitor shown in FIG. 5 may be determined depending on the cutoff frequency and how many dB the gain is.

FIG. 6 shows another circuit diagram of a low-pass filter whose gain can be switched. FIG. 6 shows a second-order low-pass filter with an RC buffer. The gain of this filter is determined by the values of the resistors R2 and R3 and can be expressed by the following equation (4).

Gain = (R2 + R3) / R2 (4)

As shown in FIG. 6, an analog switch 48 is provided between the resistors R2 and R3. The analog switch 48 is configured to turn on / off according to a switching signal from the input detector 5. When the input signal is not zero, the analog switch 48 is turned on (ON),
The gain of the low-pass filter 4 is, for example, about 40 dB. When the input signal is zero, the analog switch 48 is turned off (OFF), and the gain of the low pass filter 4 drops to 0 dB.

The resistance value of each resistor and the capacitance of the capacitor shown in FIG. 6 may be determined by the cutoff frequency and the gain to be set to dB.

As described above, in the present invention, the S / N at the time of silence is simply added to the basic structure of the delta-sigma type D / A converter by adding the simple signal detector, the resistor and the analog switch. The effect that it can be improved is obtained.

Further, in the above-described embodiment, an example using a second-order low-pass filter is used. However, the same effect can be obtained by using a third-order or higher-order low-pass filter to change the resistance (R). Of course, the effect of is obtained.

[0036]

As described above, in the D / A converter using the delta sigma modulation of the present invention, when the input signal is zero, the gain of the low-pass filter is switched according to the detection, and the existing circuit is changed. Cost and power consumption can be suppressed by maximizing the configuration and minimizing the increase in circuit scale. Even when the input digital signal is zero, D / A reduces noise due to limit cycles. A converter can be provided

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a D / A conversion device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second-order VCVS type (positive feedback type) low-pass filter.

FIG. 3 is a circuit diagram showing a second-order VCVS type low-pass filter capable of switching gain according to the embodiment of the present invention.

FIG. 4 is a circuit diagram of a basic second-order MFB type (multiple negative feedback type) low-pass filter.

FIG. 5 is a circuit diagram of a second-order MFB type low-pass filter capable of switching gain according to the embodiment of the present invention.

FIG. 6 is a circuit diagram of a second-order low-pass filter with an RC buffer capable of switching gain according to the embodiment of the present invention.

[Explanation of symbols]

1 Digital filter 2 Delta sigma modulator 3 1-bit D / A converter 4 low pass filter 5 input detector

Claims (5)

[Claims] 1. A delta-sigma modulator for delta-sigma-modulating multi-bit digital data, a D / A converter for converting digital data output from the delta-sigma modulator into an analog signal, and the D / A converter. A low-pass filter having a gain for filtering the high-frequency part of the signal output from the input device, and an input detector for detecting the presence / absence of an input multi-bit digital signal. The low-pass filter can switch a plurality of gains. And the gain of the low-pass filter is switched according to the detection output of the input detector. 2. A VCVS as the low-pass filter
2. The D / A conversion device according to claim 1, wherein a resistance component that determines a gain is switched according to a detection output of the input detector by using a low pass filter of the type. 3. A resistor for determining the gain is connected in series, one resistor is configured to be detachable by a switch, and the switch is controlled according to a detection output of the input detector. The D / A conversion device according to claim 2. 4. The D / A conversion according to claim 1, wherein an MFB type low-pass filter is used as the low-pass filter, and a resistance component that determines a gain is switched according to a detection output of the input detector. apparatus. 5. Resistors for determining gain are connected in parallel,
One of the resistors can be separated by a switch,
The D / A conversion device according to claim 4, wherein the switch is controlled according to a detection output of the input detector.