JP2002261616A - D/a conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delta sigma type D/A converter for reducing noise due to a limit cycle even when the increase of a circuit scale is held minimum and an input digital signal is zero. SOLUTION: The D/A conversion device is provided with a delta sigma modulator 2 delta-sigma-modulating multi-bit digital data, a D/A converter 3 the digital data output from the delta sigma modulator 2 into an analog signal, an input detector 5 for detecting the presence of an input multi-bit digital signal, and an analog post filter 4 for filtering the high area part of the signal output from the D/A converter capable of changing over a cut-off frequency. The cut-off frequency of the analog post filter 4 is changed over in response to the detection output of the input detector 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter for converting a digital signal into an analog signal.
The present invention relates to a D / A converter that reduces noise during silence in a D / A converter using delta-sigma modulation.

[0002]

2. Description of the Related Art Generally, a delta-sigma D / A converter converts a multi-bit digital signal to a higher sampling frequency by an interpolation filter and performs delta-sigma modulation to reduce quantization noise to a higher frequency band. Shift and reduce low frequency noise. Noise shifted to high frequencies is removed by an analog post filter.
Since the noise is shifted to a frequency band sufficiently higher than a required frequency band, a low-order filter having a gentle attenuation characteristic can be used as the analog post filter. Due to these processes, high S
A D / A converter having a / N ratio can be realized.

In recent years, digital signal processing circuits such as a delta-sigma modulation section and an interpolation filter have been used for IIR (Infinite I / O).
mpulse Response) filter is frequently used. This I
The IR filter has the advantage that the circuit scale for obtaining desired characteristics can be smaller than that of a FIR (Finite Impulse Response) filter. On the other hand, when the input signal is zero, the output does not become zero. Generates periodic noise. This phenomenon is called a limit cycle.

As a measure for preventing the limit cycle, a method of adding a dither signal is generally used. However, there is a problem that the added dither signal causes a reduction in the S / N ratio, and the maximum amplitude that can be input as a signal is a dither signal. There is a problem that the amplitude is reduced by the amplitude of

Japanese Patent Application Laid-Open No. 4-115722 discloses that the presence or absence of a digital signal as an input to a noise shaver (delta sigma modulation) is detected, and when there is no signal, the dither function is stopped and data in the noise shaver is detected. There is proposed a D / A converter configured to reduce noise by clearing.

Japanese Patent Application Laid-Open No. 11-150477 discloses that a digital delta-sigma modulation circuit, a low-pass filter circuit, a mute circuit including an operational amplifier, and a silence detection circuit are provided. There has been proposed a D / A converter configured to reduce the amplification factor of a mute circuit.

[0007]

As described above, various methods have been tried to solve the limit cycle.
Along with an increase in circuit scale, problems such as an increase in cost and an increase in power consumption remain.

In view of these circumstances, the present invention solves the problems of increased cost and power consumption by maximizing the existing circuit configuration and minimizing the increase in circuit scale. An object of the present invention is to provide a delta-sigma D / A converter that reduces noise due to a limit cycle even when an input digital signal is zero.

[0009]

SUMMARY OF THE INVENTION The present invention provides a delta-sigma modulator for performing delta-sigma modulation on multi-bit digital data, and a D / A converter for converting digital data output from the delta-sigma modulator into an analog signal. An input detector for detecting the presence or absence of an input multi-bit digital signal; an analog post-filter for filtering a high-frequency portion of a signal output from the D / A converter whose cutoff frequency is switchable; Wherein the cutoff frequency of the analog post filter is switched according to the detection output of the input detector.

A Butterworth filter can be used as the analog post filter, and the cutoff frequency can be switched by changing the capacitance or resistance of the filter.

Further, according to the present invention, a resistor is connected in parallel, one of the resistors is configured to be detachable by a switch, and the switch is controlled in accordance with a detection output of the input detector so that a resistance value is reduced. The cutoff frequency can be switched by changing the cutoff frequency.

As described above, according to the present invention, by simply adding a simple input detector, a resistor, and a switch to the configuration of the basic delta-sigma D / A converter, the S / S at the time of silence can be obtained.
The effect that N can be improved is obtained.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a D / A converter according to an embodiment of the present invention.

In this embodiment shown in FIG. 1, a multi-bit digital signal (DIN) is input at a sampling frequency fs of 19.2 KHz. Digital signal (DIN)
Is input to a digital filter 1 called an interpolation filter (interpolation filter). The digital filter 1 converts an input signal of 19.2 KHz sampling to 2.4576 MHz, which is 128 times, and removes an image signal. The digital signal converted to the high sampling frequency is provided to the delta-sigma (ΔΣ) modulator 2.

The given digital signal is reduced in bit by the delta-sigma modulator 2. Here, a 1-bit bit stream signal is generated by the secondary delta-sigma modulator 2. At this time, the quantization noise is shifted to a higher band, and the quantization noise distributed in the signal band decreases. This 1-bit bit stream signal is
The signal is supplied to the D / A converter 3, converted into an analog signal by the 1-bit D / A converter 3, and high-frequency noise is removed by the analog post filter 4. An analog output (AOUT) is output from the analog post filter 4. The analog post filter 4 is configured so that the cutoff frequency can be switched, as described later.

As shown in FIG. 1, in this embodiment, a multi-bit digital signal (DIN) is given to an input detector 5, and the input detector 5 determines whether or not the input signal is zero. When the input detector 5 detects that the input signal is zero, the input detector 5 outputs a switching signal. According to this switching signal, the cutoff frequency of the analog post filter 4 is reduced.

Since the noise to be removed is sufficiently high in the analog post filter 4, a low-pass filter having a low order can be used. Here, a secondary Butterworth filter having a flat passband characteristic is used as the low-pass filter.

FIG. 2 shows a basic circuit diagram of a Butterworth filter. The Butterworth filter is an operational amplifier 41
And resistors (R) 42, 43, capacitors (C) 44,
5 is comprised. The cutoff frequency of the Butterworth filter is determined by the values of C (44, 45) and R (42, 43) in FIG. 2 and can be expressed by the following equation (1).

Fc = 1 / (2πCR) (1)

In order to sufficiently pass through the voice band and remove high-frequency noise, the cut-off frequency is set to about 2 here.
It was set to 0 KHz. At that time, the value of C (44, 45) is 0.01 μF, and the value of R (42, 43) is 800Ω.

As described above, a multi-bit digital signal (DIN) is supplied to the input detector 5, and the input detector 5
Detects that the input signal is zero,
A switching signal is output from the input detector 5. According to the switching signal, in this embodiment, the cutoff frequency of the analog post filter 4 is reduced to about 40 Hz. By lowering the cutoff frequency of the analog post filter 4 to about 40 Hz, the signal in the audio band can be attenuated, and the noise generated by the limit cycle can be reduced.

FIG. 3 shows a configuration example of the analog post filter 4 in this embodiment. Each of the resistors 42 and 43 of the basic circuit configuration shown in FIG. 2 has two resistors arranged in parallel. A resistor R2 (42b, 43b) is arranged in parallel with the resistor R1 (42a, 43a), and the combined resistance is changed by analog switches 46, 47.

Here, the value of C (44, 45) is set to 0.01
μF, the value of the resistor R1 (42a, 43a) is 400 KΩ,
The value of R2 (42b, 43b) is set to 800Ω.

The analog switches 46 and 47 are turned on when the input signal is not zero, and turned off when the input detector 5 detects that the input signal is zero.

When the input signal is not zero, the analog switches 46 and 47 are turned on in accordance with the switching signal given from the input detector 5, and the cutoff frequency becomes approximately 20.
KHz. If the input signal is zero, the input detector 5
The analog switches 46 and 47 are turned off in response to the switching signal given by
Down to.

The cutoff characteristic of the second-order Butterworth filter is -12 dB / oct.
About -20 dB near 0 Hz, about -6 near 1 KHz
Noise removal of 0 dB is possible.

As described above, since the cutoff frequency of the Butterworth filter is determined by the capacitance (C) and the resistance (R), the cutoff frequency is switched by changing the resistance value in the above embodiment. Alternatively, the cutoff frequency may be switched by changing the capacitance.

In the above-described embodiment, an example is shown in which a second-order Butterworth filter is used. However, a configuration is used in which a capacitance (C) or a resistance (R) is changed using a third- or higher-order Butterworth filter. By doing so, it goes without saying that a similar effect can be obtained. Also, in the Butterworth filter, the attenuation characteristic becomes steep as the order increases, so that the noise cut can be further increased.

[0029]

As described above, the delta-sigma D / A converter of the present invention detects when the input signal is zero,
By switching the cutoff frequency of the analog post filter accordingly, the existing circuit configuration can be used to the maximum, and the increase in the circuit size can be minimized to reduce the cost and power consumption. It is possible to provide a delta-sigma D / A converter that reduces noise due to a limit cycle even when the signal is zero.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a D / A converter according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a basic Butterworth filter.

FIG. 3 is a circuit diagram showing a configuration of a Butterworth filter according to the embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 digital filter 2 delta-sigma modulator 3 1-bit D / A converter 4 analog post-filter 5 input detector

Claims (3)

[Claims] 1. A delta-sigma modulator for performing delta-sigma modulation on multi-bit digital data, a D / A converter for converting digital data output from the delta-sigma modulator into an analog signal, An input detector for detecting the presence or absence of a digital signal; and an analog post filter for filtering a high-frequency portion of a signal output from the D / A converter whose cutoff frequency is switchable,
A D / A converter, wherein a cutoff frequency of the analog post filter is switched according to a detection output of the input detector. 2. The D / A converter according to claim 1, wherein a Butterworth filter is used as the analog post filter, and the cutoff frequency is switched by changing the capacitance or resistance of the filter. 3. A resistor is connected in parallel, one of the resistors is configured to be detachable by a switch, and the switch is controlled in accordance with a detection output of the input detector to change a resistance value to cut the resistance. The D / A converter according to claim 2, wherein the off-frequency is switched.