JPS6292463A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make a linear transistor withstand (VCEO) high by increasing the thickness of an epitaxial layer without deepening the diffusing depth of a base region of the transistor. CONSTITUTION:An N<-> type epitaxial layer 22 is formed on the entire substrate 21, a P<+> type separating region 24 is formed, the first-fourth doped layers 34-37 doped by heat treating at this time are diffused in the substrate 21, upward diffused to the layer 22 to form the first, second buried layers 23a, 23b, a lower base leading region 33a and a buried base region 29. The P-type impurity is selectively diffused to form a base region 26 on the first insulator region 25a, and an injector region 30 and an upper base contacting region 33b on the second insular region 25b, the N-type impurity is selectively diffused to form emitter region 27 and collector contacting region 28 on the region 25a, a collector contacting region 31 and an emitter contacting region 32 on the region 25b, and electrodes are arranged on the regions.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an improvement in a semiconductor integrated circuit in which a buried base type IIL having a structure in which a substantial base region is buried and a bipolar transistor coexist.

(b) Conventional technology IIL is a logic circuit element with a lateral PNP transistor on the injection side and a reverse vertical NPN transistor on the output side, and is capable of high-speed, low power consumption operation, and can coexist with normal bipolar transistors. It has the characteristic of being able to However, since a reverse vertical NPN) transistor cannot obtain a high reverse β (reverse current amplification factor) due to its structure, a buried base type IIL with a structure in which the substantial base region is buried is used, for example in Japanese Patent Application No. 1983 -84876.

FIG. 3 shows a semiconductor integrated circuit device in which such a buried base type IIL and a normal bipolar transistor coexist, in which (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer, and (3a) is a P-type semiconductor substrate. (3b) (c) N-type first and second buried layers formed on the surface of the substrate (1); (4) the first and second buried layers;
P+ type isolation regions penetrating the epitaxial layer (2) so as to surround the second buried layers (3a) and (3b), respectively;
(5a) and (5b) are first and second island regions separated into island shapes by the separation region (4). First island area (5a)
has a P type base region (6) and an N+ type emitter region (7).
and an N-type collector contact region (8), and a bipolar N-type collector contact region (8) is formed with the first island region (5a) as a collector.
PN) constitutes a transistor.

On the other hand, the island region (5b) of plan 2 has a second buried layer (3b).
P-type embedded base region (9) embedded above and P-type injector region α formed on the surface of the second island region (5b)
Q, N+ type collector contact region α°C, N+ type emitter contact region (2), and P type that reaches from the surface of the second island region (5b) to the buried base region (9) so as to surround the collector contact region (b). A lateral PNP transistor is formed in which the injector region α1 is the emitter, the second island region (5b) is the base, and the base derivation region (c) is the collector. (5b) and second buried layer (3b)
An embedded base type IIL is configured with an inverse vertical NPN) transistor whose emitter is the embedded base region (9), and whose collector is the second island region (5b) partitioned by the base derivation region (2). are doing.

The divided second island region (5b) which becomes a collector is led out by a collector contact region (b), and the second island region (5b) which becomes an emitter is connected to a ground potential via an emitter contact region (6). (GND) is applied.

Therefore, the injector region < 10 and the base lead-out region (to) of IIL are the base region (to) of the bipolar transistor.
6) At the same time, the collector contact region (6) and the emitter contact region @ of the IIL are diffused and formed at the same time as the emitter region (7) and the collector contact region (8) of the bipolar transistor.

(c) Problems that the invention seeks to solveHowever,
In IIL, increasing the crawling of the buried base region (3b) reduces the inverse β, so the base derivation region (3b)
In order to have a structure where c) reaches from the surface of the second island region (5b) to the buried base region (9), the epitaxial layer (
2) cannot be made thicker. Therefore, the bottom of the base region (6) of the bipolar transistor and the first buried layer (3a
), and the breakdown voltage (Vcwo) could not be increased.

2) Means for solving the problem The method consists of a lower base region (33a) by diffusion and an upper base derivation region (33b) by selective diffusion from the surface of the second island region (25b), and the upper base Derived area (3
3b) and the base region of the bipolar transistor are formed simultaneously to provide a semiconductor integrated circuit in which the withstand voltage (Vco) of the bipolar transistor is increased.

(E) Function According to the present invention, the buried base region -
Since the upper base leading region (33b) and the base region (e) of the bipolar transistor are formed at the same time, the bottom of the base region (a) and the first buried layer (23a) are formed simultaneously.
) and high voltage resistance fv.
c. ) can be obtained.

(F) EXAMPLE An example of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit according to the present invention, where e]) is a P-type semiconductor substrate, @ is an N-type epitaxial layer, and (23
a) (23b) are the first and second buried layers formed on the surface of the substrate en; (c) is the first. Second buried layer (23a) (23
An epitaxial layer (a) surrounds each of b).
The P-type isolation regions (25a) and (25b) passing through are the first and 20th island regions separated into islands by the isolation region (c). The first island region (25a) has a P-type base region (
E), an N type emitter region and an N type collector contact region (C) are formed, and a first island region (25a) is formed.
A bipolar NPN) transistor is configured with the collector as the collector. On the other hand, the island region (25b) of plan 2 includes a P-type buried base region buried on the second buried layer (23b).
and a P-type injector region (1) formed on the surface of the second island region (25a), an N-type collector contact region (2), an N-type collector contact region (2), and a collector contact region C (1). A P-type base derivation region (Zeng) for deriving the formed buried base region is formed, and this base derivation region overlaps with the buried base region and spreads rumors from the surface of the substrate (1). Lower base derived region (33a) from the surface of the lower base derived region (33a) and second island region (25b) formed by
and an upper base derivation region (33b) reaching . The second island region (25b) includes a latera #PNP transistor having the injector region (7) as the emitter, the island region (25b) as the base, and the base derivation region (to) as the collector, and the second island region ( 25b) and the second buried layer (23b) as the emitter, and the buried base region as the base 1.
．． The second island area (2
5b) constitutes a buried base type IIL with a reverse vertical NPN transistor having a collector. The divided second island region (25b) which becomes the collector is led out by the collector contact region 6D, and the second island region (25b) which becomes the emitter is led out by the collector contact region 6D.
The emitter contact region (2) is located in the island region (25b) of
A ground potential (GND) is applied through the terminal.

Therefore, the injector region (to) and the upper base lead-out region (33b) of the IIL are formed by diffusion at the same time as the base region (a) of the bipolar transistor, and the collector contact region a and the emitter contact region (a) of the IIL are formed by diffusion. It is also diffused at the same time as the emitter region of the bipolar transistor.

The most distinctive feature of the present invention is that the base derivation region (c) is divided into a lower base derivation region (33a) and an upper base derivation region (33a).
33b), and an upper base derivation region (33b
) and the base region (e) of the bipolar transistor are simultaneously formed. The base derivation region (to) has a structure that reaches from the surface of the second island region (25b) to the buried base region in order to derive the buried base region and to partition the second island region (25b) which becomes the collector. However, in the present invention, since the structure is divided into upper and lower parts, the upper base lead-out region (33b) does not need to be formed so deeply. Therefore, in a bipolar transistor, the base region (h) is formed simultaneously with the upper base region (33b).
Since a sufficient distance can be maintained between the bottom and the first buried layer (23a), a high breakdown voltage ('vc,.) can be obtained.

Moreover, it is also possible to form a transistor with good high frequency characteristics by reducing the diffusion depth of the base region (e). On the other hand, in IIL, this can be derived without increasing the creep of the buried base region, so the inverse β
It is possible to increase the speed of IIL by increasing .

The method for manufacturing a semiconductor integrated circuit according to the present invention will be described below as shown in FIG.
This will be explained using (a) to (a).

First, as shown in FIG. 2, N-type impurities, such as antimony (Sb), are selectively added to the regions that will become the first and second buried layers (23a) and (23b) on the surface of the P-type semiconductor substrate υ. After forming the first and second doped layers (2) and (2) by telepositioning, a P-type layer is superimposed on the second doped layer (2) and formed in the region to become the lower base derivation region (33a). ion implantation of impurities, such as boron (B) into the third doped layer)
form.

Next, as shown in FIG. 2(B), P-type impurity ions are again implanted into the region that is to become the buried base region, superimposing on the second doped layer (T), and then the third doped layer (T) is formed.
: Form a 40th doped layer (b) with a lower concentration.

Furthermore, as shown in FIG. 2(c), an N-type epitaxial layer is formed on the entire surface of the substrate Q1) by vapor phase growth, and a P-type isolation region (c) is formed by selective diffusion. The 11th, 2nd, 3rd, and 4th elements were doped in advance by heat treatment.
The doped layers (23a) (23b) are diffused into the substrate Qη and also diffused upward into the epitaxial layer (a), forming the 11th and 2nd buried layers (23a) and (23b), respectively. ,
A lower base lead-out region (33a) and a buried base region are formed.

Then, as shown in FIG. 2(b), P-type impurities are selectively diffused to form a base region (e) in the first island region (25a).
An injector region (to) and an upper base contact region (33b) are respectively formed in the second island region (25b), and then N-type impurities are selectively diffused to form the first island region (25b).
5a) In K, an emitter region and a collector contact region (1) are formed, and in the second island region (25b), a collector contact region 0 and an emitter contact region (A) are formed, respectively.Finally, electrodes are formed on each region (Fig. (not shown) and finish.

(G) As described in detail, according to the present invention, the epitaxial layer thickness can be increased without increasing the diffusion depth of the base region (E) of the linear transistor, so that the breakdown voltage f of the linear transistor can be increased.
It has the advantage that f, , , ) can be made high. Also II
In L, the base derivation region (to) is divided into upper and lower parts, so the diffusion time is shortened, horizontal diffusion is suppressed and miniaturization is achieved, and by miniaturization, reverse vertical NPN)
This has the advantage that the IIL speed can be increased by reducing the capacitance between the base and emitter of the transistor. Furthermore, even if the base region (a) of the linear transistor is designed to be shallow, it is possible to derive the buried base region in IIL by using the upward slope of the lower base derivation region (33a) as a dog, so it is possible to derive the buried base region. It also has the advantage that it can easily coexist with other linear transistors.

[Brief explanation of drawings]

Figure 1 is a sectional view for explaining the present invention, Figure 2 (a)
3 to 3) are process cross-sectional views for explaining the manufacturing process of a semiconductor integrated circuit according to the present invention, and FIG. 3 is a cross-sectional view for explaining a conventional example. Explanation of the main drawing numbers (1) @ 1) is the P-type semiconductor substrate, (6) (c) is the base region of the linear transistor, (7) @ is the emitter region of the %'L linear transistor, (9) is the IIL embedded base area, (10(1) is the injector area of IIL, (2) G is the collector contact area of IIL, a3
(to) is the base derivation area of IIL, (33a) is the lower base derivation area, and (33b) is the upper base derivation area.

Claims (1)

[Claims] (1) A semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type formed on the substrate, first and second buried layers of opposite conductivity type buried in the surface of the substrate, and the first and second buried layers of the opposite conductivity type buried in the surface of the substrate. first and second island regions separated into islands by isolation regions of one conductivity type penetrating the epitaxial layer so as to respectively surround the buried layer; and a base, an emitter, and a collector formed in the first island region. a bipolar transistor comprising a bipolar transistor;
a buried base region of one conductivity type buried on the buried layer; a lower base lead-out region of one conductivity type formed by upward diffusion from the substrate surface overlapping the buried base region; an injector region of one conductivity type formed on the surface of the second island region and a collector contact region of the opposite conductivity type; and an injector region of one conductivity type that extends from the surface of the second island region to the lower base lead-out region so as to surround the collector contact region. an upper base lead-out region, the injector region and the upper base contact region are formed in the same process as the base of the bipolar transistor, and the collector contact region is formed in the same process as the emitter of the bipolar transistor. Features of semiconductor integrated circuits.