JPS628940B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor integrated circuit device that is equipped with a high voltage protection element to protect the high voltage element.

Generally, in a semiconductor integrated circuit device, a group of input/output high-voltage elements is formed around a chip, and a standard-voltage element group is formed inside these elements. One of the reasons why high-voltage elements are used as input/output elements is to counteract the effects of externally connected devices and static electricity, but they can still be destroyed. A protection element (circuit) is inserted between an input/output line and ground, and when an abnormally high voltage is applied to the line, the protection element breaks down and grounds the line.

By the way, an element for protecting the high voltage input/output element as described above must also have a high voltage resistance. In order to improve the withstand voltage of the protection element, for example, if the integrated circuit device is an n-channel MIS
(Metal Insulator Semiconductor) element, the protection element is formed by forming an n ^- type impurity region around an n ⁺ type impurity diffusion region. However, in this case, the withstand voltage of the protection element tends to be significantly higher than that of the high-voltage element to be protected, and therefore the high-voltage element to be protected before the protection element breaks down. Accidents often occur where the vehicle is destroyed first. In order to prevent such accidents from occurring, it may be considered that the impurity concentration of the n ^- type impurity region should be appropriately selected, but it is extremely difficult to control this.

Another conventional example is a lateral type nPn transistor shown in the cross-sectional view of FIG. This transistor has n-type regions 3D and 3S, which are opposite conductivity type regions, formed in a P-type semiconductor substrate.
Al electrodes 4D and 4S are in contact with each other. Then, a field oxide film 2 is formed on the surface of the semiconductor substrate, and a P-type channel cut region CC is formed immediately below the field oxide film 2.
is buried. Note that 5 is a PSG film.

In this lateral type nPn transistor, when a high voltage is applied to the electrode 4D, the electric field is concentrated particularly at the Pn junction end 10 of the Pn junction between the substrate 1 and the n-type region 3D, and breaks from that part first.・Causes down. Therefore, in order to make this transistor have a high breakdown voltage, it is sufficient to reduce the dose of the P-type channel cut region CC buried in contact with the Pn junction end 10. However, since the transistor serving as the protection element is manufactured together with the standard high-voltage element group, the dose amount of the channel cut region CC cannot be reduced very much due to the characteristics of the field transistor of the standard high-voltage element group. Therefore, it is not possible to make the breakdown voltage that high.

The present invention reduces the high voltage of the protection element to the above-mentioned n ^-
It is higher than a transistor having no type impurity region or a transistor having the structure shown in FIG. 1, and its protective element can be formed at the same time using the process of manufacturing other elements.

In a semiconductor integrated circuit device having a semiconductor element and a semiconductor protection element for protecting the element, the semiconductor protection element is formed in a semiconductor substrate of one conductivity type that is common to other element parts of the device. an opposite conductivity type region that forms a Pn junction with the semiconductor substrate; and a field portion that is thin enough to surround the Pn junction end and exert its influence on the vicinity of the Pn junction end when a voltage is applied. an insulating film formed on the surface of the semiconductor substrate with a channel cut region buried under the insulating film and formed apart from the opposite conductivity type region and having the same conductivity type as the semiconductor substrate; and the opposite conductivity type region. It is characterized by having an electrode that is in contact with the mold region and whose edge extends to a thin field portion of the insulating film, and an opposite conductivity type region that is close to and in contact with the opposite conductivity type region. This is achieved by providing a semiconductor integrated circuit device that achieves this goal.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a cross-sectional view of a lateral nPn transistor of a protection element according to an embodiment of the present invention. In this embodiment, an n-type region 3D, which is an opposite conductivity type region, is formed in a P-type semiconductor substrate 1, thereby forming a Pn junction. A field oxide film 2, which is an insulating film, is formed to surround this Pn junction end, and a P-type channel cut region CC is buried directly under the field oxide film 2, apart from the n-type region 3D. An electrode 7 made of, for example, polysilicon is formed in contact with the n-type region 3D, and an edge 7a of the electrode 7 extends over the field oxide film 2, and when a voltage is applied to the electrode 7, It is now possible to have this effect on the Pn junction.
Furthermore, an Al electrode 4D is in contact with the electrode 7. An n-type region 3S, which is a region of the opposite conductivity type, is provided in the vicinity of the aforementioned n-type region 3D and in contact with the Al electrode 4S. Note that the n-type region 3D and channel cut region CC are separated as shown at 10 in the figure by forming an oxide film 6 in advance. Further, 5 in the figure is a PSG film.

It will be explained that such a lateral type nPn transistor has a high breakdown voltage and that the increase in breakdown voltage can be easily controlled.

First, when a high voltage is applied to the Al electrode 4D and a reverse bias is applied to the Pn junction formed between the substrate 1 and the n-type region 3D, the Coulomb force on the edge 7a of the polysilicon electrode 7 causes the Electrons, which are minority carriers in the substrate 1 and in the channel cut region CC, are attracted to the portion of the n-type region 3D side of the channel cut region CC and are repelled by holes, so that an n-type inversion layer is formed there. be done. This alleviates the concentration of electric field on the Pn junction at the portion 10a in the figure, making it difficult to break down and resulting in a high withstand voltage.

Moreover, its breakdown voltage will not be significantly higher than that of the structure in which the above-mentioned n ^- type impurity region is formed.

Next, the manufacturing process of the embodiment shown in FIG. 2 will be explained with reference to the sectional views shown in FIGS. 3 and 4.

Refer to FIG. 3. Using a nitride film as a mask, a P-type channel cut region CC is formed by, for example, B ⁺ ion implantation on the surface of a P-type semiconductor substrate 1, and a field oxide film 2 is formed by a conventional selective oxidation method. These steps can be carried out simultaneously with the steps for standard breakdown voltage elements, such as MOS type transistors.
At the same time as the gate oxide film of the MOS transistor is formed, an oxide film 6 is formed.

Refer to Figure 4 Next, at the same time as the step of opening a window in the gate oxide film for a non-battery contact of a standard MOS transistor, the oxide film 6 on the n-type region 3D is opened.
Open the window as shown in Figure 4a. Then, at the same time as the step of forming the polysilicon gate electrode, the electrode 7 is formed. An edge 7a of this electrode 7 extends over the field oxide film 2. Also in this process n
The oxide film 6 on the mold region 3S is removed.

Then, n-type regions 3D and 3S are formed by, for example, P ⁺ ion implantation. This process is standard
This process can be performed simultaneously with the process of forming the source and drain regions of a MOS transistor. Due to the presence of the oxide film 6, this n-type region 3D is formed apart from the channel cut region CC as shown at 10 in the figure. (approximately 2 to 3μ) After that, a PSG film 5 is formed, and windows are opened at the same time as the window opening process for the source and drain electrodes.
Al electrodes 4D and 4S are formed in contact with polysilicon electrode 7 and n-type region 3S, respectively.
With the above steps, the lateral type nPn transistor shown in FIG. 2 is formed.

As explained above, the present embodiment shown in FIG. 2 can be formed simultaneously with the manufacturing process of the standard breakdown voltage element group without adding any new process.

Next, another embodiment of the present invention will be described with reference to the sectional view of FIG. The difference between this lateral type nPn transistor and the case shown in FIG. 2 is the structure of the electrode in contact with the n-type region 3D. Specifically, the central portion of polysilicon 7 is etched away and the edges 7 are etched away.
Only the part a remains, and after forming the n-type region 3D by ion implantation using the edge 7a and the oxide film 6 below as a mask, the PSG formed
As shown in FIG. 5, the film 5 is opened larger than the n-type region 3D, and the Al electrode 4D is connected to the field oxide film 2.
It is formed to extend upward.

The reason why such a structure has a high breakdown voltage is exactly the same as that of the embodiment shown in FIG.

As explained above, according to the present invention, the above-described lateral nPn transistor is used as a high-voltage semiconductor protection element that protects a high-voltage semiconductor element, and when a voltage is applied to the opposite conductivity type region of the transistor, the A conductivity type inversion layer of the substrate is formed at the Pn junction end. Furthermore, since the opposite conductivity type region and the channel cut region are formed apart from each other, the above-mentioned inversion layer is formed on the substrate surface and the channel cut region, and the carrier concentration is higher on the substrate surface and thinner on the channel cut region. Become. The effect of such an inversion layer increases the withstand voltage of the opposite conductivity type region. Further, the protection element of the present invention can be formed by the same manufacturing process as the standard voltage resistance element group.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional lateral nPn transistor. FIG. 2 is a cross-sectional view for explaining one embodiment of the present invention, and FIGS. 3 and 4 are cross-sectional views during the manufacturing process. FIG. 5 is a sectional view for explaining another embodiment of the present invention. In the figure, 1: semiconductor substrate, 2: field insulating film (oxide film) 3D, 3S: opposite conductivity type region (n-type region), 4D, 4S: electrode (Al), 7: electrode (polysilicon), 7a : Edge of electrode, CC: Channel cut area.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a semiconductor element and a semiconductor protection element that protects the element, the semiconductor protection element is formed in a semiconductor substrate of one conductivity type that is common to other element parts of the device, and the semiconductor a region of an opposite conductivity type that forms a P ⁿ junction with the substrate; and a film having a thin enough thickness to surround the P ⁿ junction end and exert its influence on the vicinity of the P ⁿ junction end when a voltage is applied. an insulating film formed on the surface of the semiconductor substrate having a field portion; a channel cut region of the same conductivity type as the semiconductor substrate buried under the insulating film and formed apart from the region of the opposite conductivity type; It is characterized by having an electrode that is in contact with the conductivity type region and whose edge extends to a thin field portion of the insulating film, and an opposite conductivity type region that is close to the opposite conductivity type region and in contact with the electrode. Semiconductor integrated circuit device.