JPS6289161A - Access method for single memory through plural cpu - Google Patents

Abstract

PURPOSE:To commonly use one DRAM by plural CPUs by converting a signal of a part of a line of an address line connecting a DRAM controller and one CPU and replacing the address of the CPU by an address of a specific range used by other CPU. CONSTITUTION:Both address lines of A19, A18 of two high order bits in an address bus 11 of 20 bits of CPU 1 are separated from the CPU 1 and a signal of high level is applied thereto. When addresses within a range from '00000 H'-'3FFFFH' outputted to an address bus 12 from the CPU 1 are inputted to a DRAM controller 3, they are replaced by the range of 'C0000 H'-'FFFFFH' and addresses of a range of '00000H'-'3FFFFH' of a DRAM 4 are used only by a CPU 2. Both the CPU 1, 2 using the same addresses '000000'-'003FFH' as vector addresses for an interruption processing can commonly use one DRAM 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an access method when a single memory is shared and used by a plurality of CPUs (central processing units).

[Prior art]

DRAM (dynamic random access memory) is often used as memory in recent years, but DR
In order to prevent the memory contents from being destroyed due to leakage current, AM
It is necessary to periodically rewrite (refresh) the memory contents, and a DRAM controller that performs this refresh is essential.

By the way, in recent years, there are multiple systems, for example, two systems of ports, and each port has the same DMA? A RAM controller that can control l has been put into practical use (
For example, the DRAM controller 8207 manufactured by Intel Corp.).

Since such an I) RAM controller has two systems of ports, one DRAM can be shared and accessed by two systems of devices. As a specific example of such a use, for example, one DRA may be used as a CPU and a controller for a display device. There are applications in which data is displayed on a display device while data processing is performed by a CPU by sharing I, and in such a case, it is easy to observe changes in data as a program is executed.

[Problem that the invention seeks to solve]

By the way, if you use the above-mentioned DRAM controller, you can use 2 CPUs with 1 DRA? 1 can be shared, and parallel processing such as, for example, performing data input processing using one CPU while processing data using another CPU becomes possible. However, both CP
If the programs in U are different, and if these programs are both loaded externally into DRAM shared by both CPUs, then it is natural that they should be
must be stored at different addresses in M. However, C
Depending on the PU, there is a CPt1 that is predetermined to use a specific address for a specific purpose, such as interrupt processing. Therefore, with ±2 CPυ that are predetermined to use such specific addresses for specific purposes, one DRAM is If the configuration is such that one DRA? Since there is a possibility that both CPUs use the same address of I, there is a problem in practical implementation.

[Means for solving problems]

The present invention has been made in view of the above circumstances,
One DRAM with two CPUs, each configured to use a specific range of addresses for a specific purpose.
If the DRAM controller and one CP
By converting the signals of some of the address lines connecting the CPU to the other CPU,
The configuration is such that the address in the specific range used by the PU is replaced with an address different from that used to access the DRAM. By adopting such a configuration, C
The present invention provides a method for accessing a single memory by a plurality of CPUs, which allows two PUs of the same ± same value to easily share one DRAM.

The present invention is connected to a DRAM controller having multiple ports for accessing one DRAM (dynamic random access memory) through separate address lines, and each has a specific address range for a specific purpose. In the method for accessing a single memory by a plurality of CPUs sharing the DRAM in a plurality of Crtl configured to be used for The address range of the DR is replaced with an address in a range different from that of the DR.
The present invention is characterized in that signals on some of the address lines of the one CPU are converted and applied to the memory in order to be applied to the AM.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 shows an example of a circuit configuration for implementing the method of the present invention.

In the figure, 1 and 2 are CPUs of the same standard, and in this embodiment, the addresses from "oooooo" to "003FFH" are predetermined as hector addresses for interrupt processing. Each has an address bus 11.21 consisting of 20-bit address lines from A0 to A19 for accessing the memory, as well as a common data bus 5 of 16 bits from DO to 015 for dynamic random - Connected to access memory (hereinafter referred to as DRAM) 4.

The memory controller (hereinafter referred to as DRAM controller) 3 for controlling or refreshing the DRAM 4 has two systems of 20-bit ports, to which the address buses 11.21 of the above-mentioned CPt 11.2 are connected. has been done. Also this DRAM
Controller 3 and both CPυ1 and 2 are connected through control lines 12 and 22, respectively, and both CPυ
The UI 2 sends and receives synchronization signals and the like when writing data to the DRAM 4 and reading data.

To Kano, M4 connects both CPt1l and CPt1l on data bus 5 as mentioned above.
2, and is controlled and refreshed by the DRAM controller 3 via the address bus 6.

Now, in the circuit configuration shown in Figure 1, the CPU
The upper two pins of the bit address bus 11, namely A19. Both address lines of AlB are separated from the CPUI and are at high level (specifically, +5 volts).
signal is given. By adopting such a configuration, “0O” output from the CPU to the address bus 12
Addresses in the range ``OOOH'' to ``3FFFFH'' are DR.
'C00OO when input to AM controller 3
It is replaced in the range of H2 to "FFFFFFH". In other words, as shown in FIG.
Addresses in the range “~”3FFFFH” are DRAM d
In the above example, it corresponds to the addresses in the range “cooooH” to “@FFFFFH”, and “oooooon’ to “”
Addresses in the range 3FFFFH" are used only by the CPU 2.

Therefore, the CPU program area contains C00OOH.
” to “FFFFFFH”, the same address “oooooo” to “00
3FFH'' as a vector address for interrupt processing, it becomes possible for both CPUs 2 to easily share one DRAM 4.

〔effect〕

As described above, according to the present invention, a plurality of CPUs of a standard that uses a fixed address for a specific purpose
One DRAM can be shared by multiple CPUs, and a smaller number of DRAMs and DRAM controllers can be used by multiple CPUs.

Note that in the above embodiment, two CPUs operate one DRA.
It goes without saying that the present invention is applicable not only to a configuration in which M is shared, but also to a configuration in which there are three or more CPUs. Furthermore, in the above embodiment, since the two CPUs use the same standard, the specific range of addresses used by both CPUs for specific purposes is the same range, but they each use addresses in different ranges. It goes without saying that the same effect as described above can be easily achieved even when using a CPU of the same standard as that used in the present invention, by appropriately selecting the address line for converting the signal.

[BRIEF DESCRIPTION OF THE DRAWINGS] The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram of a circuit in which the present invention is implemented, and FIG. 2 is a block diagram of a circuit in which the present invention is implemented.
FIG. 3 is a schematic diagram showing the relationship between addresses of U and one memory. 1.2...CPU 3...oRu+controller 4...DRAM

Claims (1)

[Claims] 1. Connected to a DRAM controller having multiple ports for accessing one DRAM (Dynamic Random Access Memory) through separate address lines, each having a specific address. A plurality of CPUs are configured to use the range for a specific purpose.
In the single memory access method by multiple CPUs sharing M, the address of one of the multiple CPUs is replaced with an address in a range different from the specific address range used by the other CPUs. A plurality of CPUs, characterized in that signals of some of the address lines of the one CPU are converted and applied to the memory in order to be applied to the DRAM.
How to access a single memory by.