JPS6288370A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS6288370A
JPS6288370A JP22912385A JP22912385A JPS6288370A JP S6288370 A JPS6288370 A JP S6288370A JP 22912385 A JP22912385 A JP 22912385A JP 22912385 A JP22912385 A JP 22912385A JP S6288370 A JPS6288370 A JP S6288370A
Authority
JP
Japan
Prior art keywords
insulating film
layer
protruded part
convex portion
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22912385A
Other languages
Japanese (ja)
Inventor
Kaoru Inoue
薫 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP22912385A priority Critical patent/JPS6288370A/en
Publication of JPS6288370A publication Critical patent/JPS6288370A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To prevent deterioration in characteristics of an FET, then ions are implanted through an insulating film, which is formed on the side wall of a protruded part, by preventing the projection of an ion beam on a heterojunction interface between a GaAs layer and an AlGaAs layer. CONSTITUTION:A pattern of a high-melting-point metal gate 6 of Mo and the like is formed. With this pattern as a mask, an N-type AlyGa1-yAs layer 4 and a non-doped AlxGa1-xAs layer 3 are selectively removed. Thus, a protruded part, which is to become a gate, is formed on the surface of a semi-insulating GaAs substrate 1. Then, an insulating film 11 is deposited on the entire surface. The insulating film 11 is etched with directivity being provided from the direction, which is vertical with respect to the surface of the substrate, by reactive ion etching using CF4. Then, the insulating film 11 is made to remain only on the side wall of the protruded part. With the protruded part and the insulating film 11 formed on the side wall of the protruded part as masks, ions are selectively implanted in the source and drain regions of an FET. S ions are used for the ion implantation.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法、特に選択ドーピングを
した半導体へテロ接合を用いた電界効果1−ランジスタ
の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a field effect transistor using a selectively doped semiconductor heterojunction.

従来の技術 N形A%!LASとGaAs のへテロ接合界面にたま
る高い易動度を有した2次元電子ガスを用いて高速の電
界効果トランジスタ(FET)が製作されており、高電
子易動度トランジスタ(HEMT)と呼ばれている。こ
の種のトランジスタでは通常G115層上のN形A7+
GaAS層を介して、2次元電子ガスと電極コンタクト
が形成されるが、N形A/GaAsと電極金属であるA
uGe /Ni / Auとの接触抵抗が比較的大きい
ため、素子性能を十分に発揮させられないという問題点
が考えられていた。
Conventional technology N type A%! A high-speed field-effect transistor (FET) has been fabricated using a highly mobile two-dimensional electron gas that accumulates at the heterojunction interface between LAS and GaAs, and is called a high-electron mobility transistor (HEMT). ing. This type of transistor usually has an N-type A7+ on the G115 layer.
A two-dimensional electron gas and electrode contact are formed through the GaAS layer, but the N-type A/GaAs and electrode metal A
Since the contact resistance with uGe/Ni/Au is relatively large, a problem has been considered that the device performance cannot be fully demonstrated.

この問題を解決する1つの方法として従来よりN形A 
/GaAs層k ;1’f 41<的に除去して、4:
#ンti人に−Gaps層に11なう力法が6えC〕れ
ている2、第2図II(、Iftl L−Cイit宋法
(′i1゛J、下に筒中に、]・1(′\ろ1゜第2図
(?L)において1Q−1下絶縁1/1CTaAs ;
l、t:板、2C[ノンド・−1GaAS層、3 &:
iノンドー7’J)(GajXAS層、4はN形A 5
yGa 1−、yAS層であ(ハA/GaAs層3とノ
ンビーフ−GaAs層2 (+’) ”−fj L−1
@合す11、’tfii (/(−、2次元電子ガス6
が形成さJl、ている、2この11(仮台−月1いて1
ず例えlrM”fc トノ高t、6’、l! 、1、’
、■金FM ’、f−16(1’−)パターンを形1j
lj l−、、さらにN形Af!yG2L+ −yAs
層4及びノンドープA、 /)(Ga 1−、XA 8
層3を高副(点4/属ゲートパターンをマスクに選IJ
(的に除去し2.11(板表面にゲーI・と々る凸部台
形成する。この凸部をマスクど17でソ・−ス・ドレイ
ン形成領域に選択的にイオンtTE人を114二つ3、 第2図(b)にJ、・いて、7t、1イ詞ン11人のイ
オンビームを示し、イオンlI゛人は例ぐ−ば70Ke
V〜160KeVの加速エネルギーで28S1 、(オ
ノを用い1X10.、”’、房のBg六鼠で百々う。8
Q−4イオン/1人され/ζ領域を示す。(7かる後、
例えば850’(:。
One way to solve this problem has traditionally been to
/GaAs layer k; 1'f 41<, 4:
# For those who want to know - Gaps layer has 11 force methods 6eC] 2, Fig. 2 II (, Iftl L-Cit Song method ('i1゛J, below in cylinder,]・1('\Ro1゜In Figure 2 (?L), 1Q-1 lower insulation 1/1CTaAs;
l, t: plate, 2C[nondo-1GaAS layer, 3&:
inondo7'J) (GajXAS layer, 4 is N type A 5
yGa 1-, yAS layer (HaA/GaAs layer 3 and non-beef-GaAs layer 2 (+') ”-fj L-1
@ Combine 11, 'tfii (/(-, 2-dimensional electron gas 6
is formed Jl, is, 2 this 11 (temporary stand - month 1 and 1
Example lrM"fc Tono height t, 6', l!, 1,'
, ■ Gold FM', f-16 (1'-) pattern shaped 1j
lj l-,, and further N-type Af! yG2L+ -yAs
Layer 4 and non-doped A, /) (Ga 1-, XA 8
Layer 3 is high secondary (point 4/select gate pattern as mask IJ
(2.11) (2.11) Form a convex base on the board surface. Using a mask 17, selectively inject 114 ions of ion tTE into the source/drain formation region. 3. Figure 2(b) shows an ion beam of 11 people with J, 7t, and 1I, and the ion beam of 11 people is, for example, 70Ke.
28S1 with an acceleration energy of V ~ 160KeV, (1X10. using an ax, "', hundreds of Bg six mice in a bunch. 8
Q-4 ion/one person/ζ region is shown. (After 7 days,
For example, 850' (:.

1o1:′t・〜20う′fに′)ア:−・−ルを、A
s盾四囲気中し7ぐは不活1牛カス雰囲気中“Cf’i
なうど、71人さit 4=S1 か′山、旬言′白に
C゛占1’t +’i、されN′月モモGaAsi7i
 hfi sか形tJi σノ1/)。1,7かる俊、
AuG3 /Ni  Auより々るオ・−ミック市、極
10をy1ソ成1.、’FITか作製されイ)。
1o1:'t・~20u'fni') A:-・-r, A
s shield 4 circles in air 7 inactive 1 cow scum atmosphere “Cf'i
Now, there are 71 people.
hfi s or form tJi σノ1/). 1,7 Karushun,
AuG3 /Ni Au from Au-Mic City, Pole 10 to y1 Seo Sei 1. , 'FIT was created).

発明か解決し、。l、つとする問題点 It i:(7) ’Jjr−来7k ”’l’:間j
i!−rl トナ/、)ツバ、ffi 2 M (b)
If(、L−いて0印で小し−7(Aの領吠の;坊処1
11j (アコ−・−ル)体の!7.!、面状態である
3、JGaAs l!−: GaAs (7)!4%而
イ面1i1hにSlの:’i′:冑農度f−]ンl(−
人4ニイ■ない熱処1iJを1f々うと、A/+ 、、
1−Gaの用II拡1)々かiL L:、 、’+Y 
IfiiにAlAsのセル比の小さいAgGaAs層が
形成さiLるiH,とが一般に知られ−CいZ)。11
−)で第2図(b) c7) A領域では(」ンt[人
と熱処理の二I ’、 ’t)’iiにより、 GaA
SとAgGaAsのj、+ij面が急(19−Ci: 
(iす、ノンドープGaAs層2の人iNi”i (n
ilにAjGaASか形成され子〕ことになる。このよ
うなら、とかイILると、A領域におV)る2次九電子
ガスの生イ/農度と活動…の低トを引き1.・こし、こ
の領域の抵抗か贈入することになる33fn−って、F
ETのソース抵抗が増大シ、2、素子特性が悪化するこ
とに存る。。
Invent or solve. l、One problem It i:(7) 'Jjr-7k ``'l': Between j
i! -rl Tona/,) Tsuba, ffi 2 M (b)
If (, L- is 0 mark and small-7 (A's territory; Bodokoro 1
11j (Acor--L) body! 7. ! , 3, which is a surface state, JGaAs l! -: GaAs (7)! 4% and 1i1h of Sl: 'i': 冑 Agriculture f-]nl(-
When I went to 1 iJ of heat treatment without 4 people, I got A/+.
1-Ga II expansion 1) or iL L:, ,'+Y
It is generally known that an AgGaAs layer with a small cell ratio of AlAs is formed in Ifii (iH). 11
-) in Fig. 2(b) c7) In the A region, GaA
The j and +ij planes of S and AgGaAs are steep (19-Ci:
(iS, non-doped GaAs layer 2)
AjGaAS is formed on il. If this is the case, then subtract the lower value of the secondary nine-electron gas V) in region A/agricultural rate and activity...1.・So, 33fn-, which will be a gift of resistance in this area, is F.
2. The source resistance of the ET increases, and the device characteristics deteriorate. .

本発明は従来世1−CtIl’、べた1つ4)AgGa
As層どGaAs層の界面にイオンビーム、か照射さI
’lるこ、、]fにより生じる熱処r:1+++’、y
7= r7tc :t==けるAeとCr a  (1
) 1117j拡散をなくし、素r4着/Iの悪化を直
重L7ようとするものである。
The present invention is based on the conventional 1-CtIl', solid 4) AgGa
The interface between the As layer and the GaAs layer is irradiated with an ion beam.
Heat treatment caused by 'lruko, ,] f: 1+++', y
7= r7tc : t==Keru Ae and Cr a (1
) 1117j It is intended to eliminate the diffusion and reduce the deterioration of the raw r4/I to the direct weight L7.

問題点を解メツしする/ξ、l/)の手段本発明はソー
ス・ドレイン領」・・kl[ニ成時のイオン注入r: 
+4.:の際に、A(!GaAS層とGaAS層の界面
4・絶縁膜でんうこ)−VCより、イオンビームがW面
に照射さ才することを[IT)屯するものである。
Means for solving the problem /ξ, l/) The present invention is directed to the ion implantation r during formation of the source/drain region.
+4. : At this time, the ion beam is irradiated onto the W surface from A (!interface 4 between the GaAS layers and the insulating film) -VC.

作  用 この」二うな不発fillの力法でi、LW面を覆った
絶縁膜によ−’ ” S 、、l: R〔:冑面にイ」
ンビームが照射されるのを防ILでき、素子’l’jr
 l’l−の悪化を直重することができる。
The action of this ``secondary unexploded fill'' method is to use the insulating film that covers the LW surface.
It is possible to prevent IL from being irradiated with the beam, and the element 'l'jr
The deterioration of l'l- can be directly affected.

実施例 本発明の一実施例を第1図(C」:り詳しく訝1明する
。第1図(a) t=こ1・・いて、11丁半絶縁性G
aAs基板、2はII%厚が0.6〜1.071m (
7)ノンドープG a A s層、6 ′\− 3は膜厚がO〜3oO入のノン′ドープAt!xGa、
Embodiment An embodiment of the present invention is explained in detail in Figure 1 (C).
aAs substrate, 2 has a II% thickness of 0.6 to 1.071 m (
7) Non-doped GaAs layer, 6'\-3 is non-doped At with a film thickness of O~3oO! xGa,
.

As層、4はN JfニA、 1yGa1. As層を
であり、A/!xGa、−XAsAs層ノンドープGa
As層2のW面に、2次元電子ガス5か114成され−
でいる。従来法と同様に1ず(+lJ 、i、ばMoな
どの高融点金属ゲート (J、q〕、F 余 白) 6のパターン’:c形成し、このパターン%ニー、71
区りとして、N形A7!yG町−y A、3層41.・
1!び2ノ′−1−ノA /)(Ga 1.、、、XA
S層3 ’+: i、’!’: J)く的に除ノ、17
、駄イ+<、7面にゲー 1・となる凸r’+lI k
: Iし1戊−J/)。
As layer, 4 is N Jf Ni A, 1yGa1. The As layer is A/! xGa, -XAsAs layer non-doped Ga
A two-dimensional electron gas 5 or 114 is formed on the W plane of the As layer 2.
I'm here. Similarly to the conventional method, a pattern of 1 (+lJ, i, high melting point metal gate such as Mo (J, q), F margin) 6': c is formed, and this pattern %knee, 71
As a ward, N type A7! yG Town-y A, 3rd floor 41.・
1! and 2 no'-1-A /) (Ga 1.,,,XA
S layer 3 '+: i,'! ': J) Kuniyuki no, 17
, no+<, convex r'+lI k with game 1 on the 7th side
: Ishi1戊-J/).

次に、全曲に膜i)7: 、’ハ1600へ一3000
人の1m41縁膜114扱ii″:すイ)(!″1′3
1図(bi ’II 、 &/!縁膜11J−しては、
5102膜、 Si3N4膜などを用いた。(かる後、
絶縁膜11をCF4のリアクj−、イー]fオニ、−1
−ノチンク(/(二、17す、11(扱と薗1に看し、
中1白乙:ノノ向31 り方向f1をもた+、”T −
(’ :” :y 4ンク?r ■i々つと、凸部の側
壁にのみ絶ft1lP 1iを残す(二、I−がてきる
。、ζ−の凸部と、ll1口rl(1ill 11.’
?に形成さJした絶縁膜11苓、マスクとして、FET
のソース・ド12イン領域に選択的にイオン注入ri:
 f”’r h、う3.第1図(C) 4(−おいて、
7U1イオン江人のfオンピーJ・を小(、て」、・す
、8Q−1イオン江人領域を小す。イオン11−人(〆
1.70 K6V〜16oKeVの!川り中エ ネル 
ギー−C8(硫古゛()−イ Aン含・1\1014 
踊の7[人[1+でt1々ッf、、oS 、、rオンを
用いた理由(,1、t+−人後のアニールによってSの
拡散が生じ、−次〕■、電イガスとN −’ (jrl
 F4−’Iの12、続か簀(1,にイ「レケ、ぐ一?
J /ζめ、絶縁膜11の(黄ツノ向の膜112t (
i’: 、ll、ど)−’、?:にシし?[j1了ガス
6とN1  領1或の′l)1雛介: i、:)配、)
1ずに−Jむから了あ4+3.、、(−Aンt+べのイ
オ、神と1.てSとSlを同萌に用い−CN 領域のに
血ギ−・リアi!’+’k W k・−、)t7さ−け
るc、1−も川RL−Cある0、1′オンL1人後、A
+(す1埋(アニニ・ 〕L)’tr: 肖なっ−7”
 イAンハー人I−5,たs D′J〔r < t /
こは、SJ  Si几ド「)4・電気的に211’l化
−4:!71.め、同時にSハic r’c 11ム散
−J (i N”GaAs層9を形成1−2.14次兄
71テ了カス6 clN”’領域を接続、−する1、(
第1図Ld) ) t+6 (b:に、AuGe、、/
NiAu  の」・−棗ノク電極10庖・形成し2シン
ター全付4ニーで第1[ツ1(e)のFETが作’J’
J d 7’L Z) (第1図(0)。
Next, the film i) 7: 'Ha 1600 to 13000 for all songs
Human 1m41 Membrane 114 treatment ii″: Sui) (!″1′3
Figure 1 (bi 'II, &/! Membrane 11J-)
5102 film, Si3N4 film, etc. were used. (Afterwards,
The insulating film 11 is made of CF4 reactor j-, e] f oni, -1
-Notinku (/(2, 17su, 11
Junior High 1 Hakuotsu: Nono Muki 31 with direction f1 +, "T -
(':”:y 4ink?r ■i), leaving an absolute ft1lP 1i only on the side wall of the convex part (2, I- comes., ζ- convex part, ll1 mouth rl (1ill 11. '
? The insulating film 11 formed on the FET is used as a mask.
Selective ion implantation into the source/domain region of ri:
f"'r h, U3. Figure 1 (C) 4(-,
7U1 ion Ehito's fonpi J. is small (,te'',・su, 8Q-1 ion Ehito area is small.Ion 11-person (〆1.70 K6V ~ 16oKeV! River Rinaka Energy
G-C8 (sulfur ゛()-i A-in included・1\1014
Dance 7 [Reason for using t1f,,oS,,r-on in 1+ (,1, t+- annealing after human causes diffusion of S, -next]■, electric gas and N- '(jrl
F4-'I's 12, continued (1, ni ``reke, guichi?''
J /
i': ,ll,d)-',? :Nishishi? [J1 Gas 6 and N1 Region 1'l) 1 Hinisuke: i, :) Kai,)
1 without -J Mukara 4+3. ,,(-Ant + Ben's Io, God and 1. Use S and Sl at the same time - CN area's blood-rear i!'+'k W k-,) t7 search c, 1-also river RL-C 0, 1'on L1 person later, A
+ (su1 bury (anini・) L)'tr: Porta-7”
Ianhaan I-5, s D'J [r < t /
This is the SJ Si process ()4 electrically 211'l-4:!71., and at the same time the SJ Si'c 11m dispersion-J (iN') GaAs layer 9 is formed 1-2. .14 Second brother 71 Terekasu 6 clN"' connect the area, -1, (
Figure 1 Ld) ) t+6 (b: AuGe, /
10 pieces of NiAu electrode are formed and the 1st (e) FET is made with 4 pieces of 2 sinter.
J d 7'L Z) (Figure 1 (0).

1プ[−の実施例の要点はゲートJ−なイ)凸部の側壁
に絶縁膜を形成1−8、イオンl−1人の1歴の照Q、
Iじ・−1・がGaAS層とJJGaA、s層のへテロ
接合!ifi″、面にあた1°)ない1、うに・するこ
Jと、注入イオンに3y、Hいで、熱処理の際に二次ノ
1−4電工カスと(Aンt1、人により形成したN G
aA、s領域を、Sの(黄方向拡散を用いて4?、続す
ることであり、熱処理の力θ、や高融点金属層の神類に
1(l・昌i!介加えるものでは7+’、 17)。
1P [-The main point of the example is gate J-A) Forming an insulating film on the side wall of the convex part 1-8, Ion L-1 person's 1-history light Q,
Iji-1 is a heterojunction between GaAS layer, JJGaA, and s layer! ifi'', 1°) not on the surface, 1, sea urchin, 3y, H on the implanted ions, secondary 1-4 electrician scum (Ant1, formed by humans) during heat treatment. NG
The aA, s region is defined as S (4? using yellow direction diffusion), and the heat treatment force θ and the refractory metal layer are added to 1 (l・Chang i! Intervention is 7+ ', 17).

1だ本実施例1ノ+A77GaAs層のjJ!AS ’
(ルI:b、 XおよびyQ−1I[,0,2x、y 
−0,8の範囲を一月11)た。実施例でij N−/
ヤンネルのFETについ−Cζl)べたが、Pチャンネ
ルのI易aも同様て゛あり、この場合、Beか不純物と
して用い11月1ろ。
1 This Example 1 + A77 GaAs layer jJ! AS'
(Le I:b, X and yQ-1I[,0,2x,y
-0.8 range in January 11). In the example, ij N-/
As mentioned above about Jannel's FET, the same applies to P-channel I/A, and in this case, Be or Be is used as an impurity.

−また、−1述17/(一実施例−rh(、tイン喧ン
t14人のイ」ン伸にSイオンを加えてはいるか、Sフ
イ、/l’ >”d: l−11いない場合は、次のよ
うにイー「4:うことにより、Sjイ副ンたけでも実施
できる。 −1’ 、/i:わち、Nli縁膜11中に
SやSsの不純物ヲI丙当な量l烈加1″〕1C才、9
1711人後の熱処理に、に−j″にれらの・1ミ純物
がGaAs層中へ拡j1夕し、N形GaAs層を凸部1
111壁の下ノCraA、S F(j分に形IJkす/
)のでit、ti+しにくい$1イメンをイオンl−1
人のイオン伸に用いでも一4次元電−fガスとN”Ga
As層が接U1:されることに4、る。
-Also, -1 mentioned 17/(one example-rh(, t-in-den-t14 people's in-density), S-ion, /l'>”d: l-11 not In this case, it can also be carried out by adding Sj by substituting Sj as shown below. Quantity l retsuka 1″〕1C year old, 9
During the heat treatment after 1711 hours, the pure impurities spread into the GaAs layer, causing the N-type GaAs layer to form a convex portion 1.
111 Under the wall CraA, SF (shape IJk in j minute /
), so it, ti + difficult to do $1 Imen is ion l-1
Although it is used for human ion expansion, four-dimensional electron-f gas and N''Ga
4. The As layer is in contact with U1.

PチャンネルFETの(結合に(,1、絶縁1漠11中
にZnなと゛をI念力[ド1れ(丁よい。
For the coupling of the P-channel FET, add Zn in the insulation layer 11 (just enough).

発明の効果 本発明に、1’: fl、 rJ:凸部側壁に形成され
た絶縁膜によりイ;tン()人のp2に、GaAs層と
A6GaAs 層のへプロ接合W面にイーインヒートが
I!((、fl、tされることを17+月1できイ)の
て゛、イオン汀人後の熱処J叩による凸部両端における
一二次元電−J′カスの7農度、易動度のイル下を抑制
でき、FETの71!J性劣化かイ1じない3.
Effects of the Invention In the present invention, 1': fl, rJ: Due to the insulating film formed on the side wall of the convex portion, heat is generated on the p2 of the GaAs layer and the A6GaAs layer on the heprojunction W surface of the GaAs layer and the A6GaAs layer. I! ((, fl, t can be done 17+ months)), the 7 degrees and mobility of the 12-dimensional electric current at both ends of the convex part due to the heat treatment J's beating after ion treatment. 3. It is possible to suppress the 71!J characteristic of the FET.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(l;1本発明の一実施例に13’ける半導体装
11なの製造方法4−説明ずろための二「稈断面図、第
2図は従来の製J青)J法を説明するための下1.Ji
l断面図である。、 1・・・・・・)1′絶縁(/l GaAs−t、を板
、2・・・・ノンドーゾ□eaAs層、3−=−ノンド
ープ’ A 1xGa j−、XAS層、4・・・N形
A/+yGa1yA8層、6・・・・・−次元電fガス
、6・・・・・・篩融点金属ゲート電極、7・・・・・
イオンビーム、8・・・・イオンt[大領域、9・・・
・・・NGaAs層、10・・・・オーミック電極、1
1・・・・・・絶E* 膜。 代理人の氏1 −4v理二1 中 尾 1政 男 (・
−jか1名第1図 第2図
Figure 1 (1; 1 Method of manufacturing a semiconductor device 11 according to an embodiment of the present invention 4-Explanation 2) Cross-sectional view of the culm, Figure 2 is a conventional manufacturing method. Under 1.Ji
1 is a sectional view. , 1...) 1' insulation (/l GaAs-t, plate, 2... non-doped □eaAs layer, 3-=-non-doped' A 1xGa j-, XAS layer, 4... N-type A/+yGa1yA 8 layers, 6...--dimensional electric f gas, 6... Sieve melting point metal gate electrode, 7...
Ion beam, 8... Ion t [large area, 9...
...NGaAs layer, 10... Ohmic electrode, 1
1... Absolute E* membrane. Agent Mr. 1 -4v Riji 1 Masao Nakao (・
-J or 1 person Figure 1 Figure 2

Claims (2)

【特許請求の範囲】[Claims] (1)GaAs層上に膜厚が0〜300Åのノンドープ
Al_xGa_1_−_xAS層及び第1の導電形のA
l_yGa_1_−_yAs層が順次形成された構造を
有する半導体基板の表面に、高融点金属ゲート電極を形
成する工程と、前記高融点金属ゲート電極をマスクとし
て、前記半導体基板の表面より前記ノンドープAl_x
Ga_1_−_xAs層までを選択的に除去して凸部を
形成する工程と、全面に絶縁膜を被着後、前記半導体基
板表面に対して垂直な方向より前記絶縁膜をドライエッ
チングにより除去し、前記凸部側壁のみに前記絶縁膜を
残す工程と、前記凸部及び凸部側壁に形成された前記絶
縁膜とをマスクとして、ソース・ドレイン形成領域に選
択的に前記第1の導電形の不純物をイオン注入した後、
熱処理を行なう工程を含んでなる半導体装置の製造方法
(1) A non-doped Al_xGa_1_-_xAS layer with a film thickness of 0 to 300 Å on the GaAs layer and a first conductivity type A
forming a high melting point metal gate electrode on the surface of a semiconductor substrate having a structure in which l_yGa_1___yAs layers are sequentially formed; and using the high melting point metal gate electrode as a mask, the undoped Al_x is applied from the surface of the semiconductor substrate.
A step of selectively removing up to the Ga_1_-_xAs layer to form a convex portion, and after depositing an insulating film on the entire surface, removing the insulating film by dry etching from a direction perpendicular to the surface of the semiconductor substrate, a step of leaving the insulating film only on the sidewalls of the convex portion; and using the convex portion and the insulating film formed on the sidewalls of the convex portion as a mask, selectively adding impurities of the first conductivity type to the source/drain forming region; After ion implantation,
A method for manufacturing a semiconductor device including a step of performing heat treatment.
(2)絶縁膜に第1の導電形の不純物が添加されている
特許請求の範囲第1項記載の半導体装置の製造方法。
(2) A method for manufacturing a semiconductor device according to claim 1, wherein an impurity of a first conductivity type is added to the insulating film.
JP22912385A 1985-10-15 1985-10-15 Manufacture of semiconductor device Pending JPS6288370A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22912385A JPS6288370A (en) 1985-10-15 1985-10-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22912385A JPS6288370A (en) 1985-10-15 1985-10-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6288370A true JPS6288370A (en) 1987-04-22

Family

ID=16887105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22912385A Pending JPS6288370A (en) 1985-10-15 1985-10-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6288370A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011077516A (en) * 2009-09-07 2011-04-14 Sumitomo Chemical Co Ltd Field-effect transistor, semiconductor substrate, and method of manufacturing field-effect transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011077516A (en) * 2009-09-07 2011-04-14 Sumitomo Chemical Co Ltd Field-effect transistor, semiconductor substrate, and method of manufacturing field-effect transistor

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