JPS6285530A - Control system for transferring serial data - Google Patents

Abstract

PURPOSE:To eliminate the time loss produced by the transfer of data between memories by setting the start address and the range for transfer of data in response to the logical address of an information processor and transferring data between the processors of set areas. CONSTITUTION:The interface devices 1500, 2500, 3500 and 4000 are connected to a loop type serial data transmission line as nodes and then driven by the information processors 1000, 2000, 3000 and 4000 respectively. These processors have the same constitution and the processor 1000 is formed as follows. That is, the primary part of the processor consists of an information processor adaptor 1010, a logical device 1020 and a main storage 1030. In a data output mode a transfer address and a transfer range are set by an output command given from the device 1020 and by means of a main memory output address setting means 210 set in the adaptor 1010. Then data are transferred. In a data input mode a setting means 220 is actuated by an input command given from the device 1020 and the data are transferred by a transfer means 180.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial data transfer control system, and particularly to a logical path in serial data transfer.

[Conventional technology]

Conventionally, in this type of serial data transfer control method, the destination address and source address of a branch-type serial data transmission line or loop-type serial data transmission line are set to the addresses of the interface device connected to the transmission line. The address of the information processing device connected to the interface device was not set.

[Problem that the invention seeks to solve]

In the conventional serial data transfer control method described above, each information processing device has only one logical bus, so each information processing device prepares a transfer buffer for input and output, and when outputting, it Data is first transferred from the memory to the buffer memory inside the information processing device, and the destination information processing device that receives the data via the serial data transmission path also needs to transfer data from the buffer memory to the memory. There is a drawback.

An object of the present invention is to directly transfer data from a predetermined storage area of a source information processing device to a predetermined storage area of a destination information processing device, thereby reducing time loss due to inter-memory transfer of data within the information processing device. An object of the present invention is to provide a serial data transfer control method that can reduce the number of serial data transfers.

[Means for solving problems]

In the serial data transfer control method of the present invention, a plurality of information processing devices are connected to a serial data transmission line via an interface device provided for each information processing device, and a flag,
destination address, source address, control information, data,
Serial data that transmits and receives data with a command frame that includes a frame check sequence and a flag, and transfers said data by responding with a response frame that includes a flag, a destination address, a source address, control information, a frame check sequence, and a flag. In the transfer control method, the destination address is made up of an address of a destination interface device and a logical address of an information processing device, and the source address is made up of an address of a source interface device and a logical address of the information processing device; an input transfer control means for setting a transfer start address and a transfer range of input data corresponding to a logical address of the information processing device to transfer the input data; and an output corresponding to the logical address of the information processing device. and output transfer control means for setting a data transfer start address and transfer range to transfer the output data.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an information processing device for realizing the serial data transfer control method of the present invention. The main parts of this information processing device 1000 include an information processing device adapter 1010, a logical device 1020, and a main storage device 1030.

The information processing device adapter 101O includes an encoder 110,
Decoder 120, address control code adding means 130, address deletion control code decoding means 14
0, output FIF0150, input FIFO160, output transfer control means 170, input transfer side jB means 180, output control table 190, input control table 200, main memory output address setting means 210, main memory input address setting means 220, command input/output It is composed of a microprocessor (hereinafter abbreviated as μP) 240, a read-on memory (hereinafter abbreviated as ROM) 250, a random access memory (hereinafter abbreviated as RAM) 260, and a transfer control means 270. .

FIG. 2 shows an example of a serial data transmission path to which the serial data transfer control method of the present invention is applied, in which a plurality of interface devices 1500, 2500, 3500, and 4 as nodes are connected to a loop-type serial data transmission path.
500 are connected, each interface device 1500.2
500. Information processing device too at 3500 and 4500
o.

2000, 3000 and 4000 are connected respectively.

FIGS. 3 and 4 each show an example of serial data output by a person in the serial data transfer control system of the present invention. Serial data consists of a command frame for transferring data and a response frame indicating a response to this command frame. The command frame shown in Figure 3 indicates a flag (F), a destination interface device address (IFDA), a source interface device address (IFSA), whether it is a command frame or a response frame, and whether it is an input or output frame. Control code (CTL), information processing device logical address (LA), data (i), cyclic redundancy check (CR)
C) Frame check sequence (Fe2
) and a flag (F). The response frame does not have the data (1) portion of the command frame, and the control code (CTL) indicates that it is a response frame.

Furthermore, the command frame and response frame shown in FIG. 4 are different from the command frame and response frame shown in FIG. 3, except that the control code (CTL) and information processing device logical address (LA) are switched. It goes without saying that such command frames and response frames may be used.

5 and 6 are diagrams showing the data structures of the output control table 190 and the input control table 200 shown in FIG. 1, respectively. The output control table 190 has pointers 0 to n for information processing device logical addresses (LA) O to n, and an arbitrary pointer indicates a storage location run of an output control block necessary for frame transmission.

The output control block contains the destination interface device address (IFDA), the source interface device address (
IFSA), control code (CTL), transfer start address, transfer range, etc.

On the other hand, in the input control table 200, there are O-n combinations of transfer permission bits and pointers for information processing device logical addresses (LA) 0 to n, and if the transfer permission bit is set to "l", Enables input transfer and indicates the storage location of the input control block for any pointer.
The input control block is composed of a transfer start address, a transfer range, etc.

Next, the operation of the serial data transfer control system of this embodiment configured as described above will be explained.

In the case of data output, an output command is first issued from the logic device t1020 via the signal line 21, and this output command is set in the command input/output means 230. Then, an interrupt is applied to the μP240 via the signal line 22, and the μP24
0 processes the output command based on the contents of the ROM 250. The output control table 190 shows that μP 240 is RA
An output control block converted into a format convenient for the information processing device adapter 1010 is written using the work area of the M260. There are two types of output control blocks: one that is created in advance using a command, and one that is created using a transfer command and then transferred, but here it is assumed that it has been created. In response to a command from the μP 240, the output transfer control means 170 receives the destination interface device address (I
FDA), Source Interface Device Address (IFS)
A) and the control code (CTL) are read out via the signal line 13 to the address control adding means 130.
At the same time, the transfer start address and transfer range read from the output control table 190 are set in the main memory output address setting means 210 via the signal line 17,
Start the transfer.

Data from main memory 1030 is transmitted through signal lines 20 and 1
6 to the output F[FO 150, and when the output transfer control means 170 activates the transfer via the signal line 15, it is input to the address control code addition means 130 via the signal line 14. The address control code adding means 130 selects the destination interface "4".
1 address (IFDA), source interface device address (IFSA), control code (CTL), and information processing device logical address (LA) are data (1)
and is passed to the encoder 110 via the signal line 12. Encoder 110 performs parallel/serial conversion of parallel data into serial data, adds a flag (F) to the beginning and end of the serial data, and sends it to source interface device 1500 via signal line 11 as a command frame.

A response frame as a response to this command frame is transmitted from the source interface device zisoo to the signal line 5.
1 to the decoder 120, where the flag (F) is deleted and the data is subjected to serial/parallel conversion. The converted parallel data is sent to the address deletion control code decoding means 140 via the signal line 52, where it is recognized as a response frame and data output for one frame is completed.

In the case of data input, from the logic device 1020 to the signal line 21
An input command is issued through the command input/output means 230, and this input command is set in the command input/output means 230, as in the case of data output. The interrupt is notified to μP240 via 22, and μP
240 begins processing. The input control table 200 includes input control blocks in which input transfer information is written. There are two types of input control blocks: one that is prepared in advance before transfer, and one that is created by a transfer command and then transferred.Here, the former will be explained. In response to an instruction from the μP 240, the input transfer control means 180 transfers the information processing device logical address (
Set the transfer permission bit to the pointer corresponding to LA) to “1”.
Set to . As a result, when a command frame with the information processing device logical address (LA) k arrives on the signal line 51, input transfer becomes possible.

When a command frame with an information processing device logical address (LA) k arrives on the signal line 51, the flag (F) is deleted by the decoder 120, and the serial data is converted into serial/parallel data. The converted parallel data is passed to the address deletion control code decoding means 140 via the signal line 52, and is sent to the destination interface device address (IFDA).
, source interface device address (IFSA)
, control code (CTL) and information processing device logical address (LA) are separated. Also, when the control code (CTL) is interpreted as a command frame, the information processing device logical address (LA) is
It is sent to the input transfer control means 180 via I53.

The input transfer control means 180 uses the information processing device logical address (
LA) Read the transfer start address and transfer range of the input control block to the pointer from the input control table 200 via the signal line 58 based on k, and set them in the main memory input address setting means 220 via the signal line 57. , initiates the transfer.

On the other hand, address deletion control code decoding means 140
The data from which the address and control code have been deleted is sent to the input 1'1F0160 via the signal line 54, and the input FIFO 160 and main memory input address setting means 220 perform input transfer control via the signal lines 55 and 57. When the transfer is activated by the means 180,
Data is transferred to the main memory device 103o via the signal line 60 using the transfer start address and transfer range specified in the main memory input address setting means 220.

Based on the result of the transfer control, the μP 240 gives a command to the transfer control means 270 via the signal &I22, and the transfer control means 2
70 creates a control code (CTL), and processes the destination interface device address (IFDA), source interface device address (IFSA), and information processing of the command frame obtained from the address deletion control code decoding means 140 via the signal line 59. The device logical address (LA) is supplied to the address control code adding means 130 via the signal line 19. The address control code addition means 130 sends the data to which these addresses and control codes have been added to the encoder 110 via the signal line 12, and the encoder 110 receives the flag (
F) is further added and the response frame is route 18 line 1.
1 to the destination interface device 1500 in response to the command frame.

〔Effect of the invention〕

As explained above, the present invention sets a transfer start address and a transfer range for data transfer in accordance with the logical address of an information processing device, and data transfer between information processing devices is directly defined by these transfer start addresses and transfer range. By performing the transfer between the designated areas, there is an effect that transfer between the buffer memory and the memory within the information processing apparatus can be omitted.

Further, by chaining logical addresses multiplexed, large-capacity transfer can be easily performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an information processing device for realizing a serial data transfer control method according to an embodiment of the present invention, and FIG. A block diagram showing an example of a data transmission path. FIGS. 3 and 4 are diagrams showing the data structure of a command frame and a response frame, respectively. FIG. 5 is a diagram showing the data structure of an output control table. FIG. 2 is a diagram showing the data structure of an input control table. In the figure, 110...encoder, 120...decoder, 130...address control code adding means, 140...address deletion control code decoding means, 150...output FIF○, 160...input FIFO1 170... Output transfer control i11 means, 180... Input transfer control means, 190... Output control table, 200... Input control table, 210... Main memory output address setting means, 220
...Main memory input address setting means, 230 ・
... Command output means, 240 ... Microprocessor (μP), 250 ... Read only memory (ROM), 260 ... Random access memory (RAM), 270 ... Transfer control means, 1000.2000 , 3000.4000... Information processing device, 1010... Information processing device adapter, 1020...
Logical device, 1030... Main storage device, 1500.2500, 3500.4500... Interface device. Agent: Patent Attorney Susumu Uchihara\, , '2

Claims (1)

[Claims] A plurality of information processing devices are connected to a serial data transmission path via an interface device provided for each information processing device, and a flag, destination address, source address, control information, data, and frame check are provided. Serial data transfer control that transmits and receives data using a command frame that includes a sequence and a flag, and transfers the data by responding with a response frame that includes a flag, a destination address, a source address, control information, a frame check sequence, and a flag. In the method, the destination address is made up of an address of a destination interface device and a logical address of an information processing device; the source address is made up of an address of a source interface device and a logical address of the information processing device; and the information an input transfer control means for setting a transfer start address and a transfer range of input data corresponding to a logical address of a processing device to transfer the input data; A serial data transfer control method, comprising: output transfer control means for setting a transfer start address and a transfer range to cause the output data to be transferred.