JPS6280716A - Reset circuit for backup - Google Patents

Abstract

PURPOSE:To maintain the contents of a RAM even if a power supply is turned off or a power supply voltage is instantaneously changed by executing memory backup operation when the power supply is turned off, and executing prescribed reset operation when the power supply is turned on. CONSTITUTION:If a dropped voltage level is reduced less than the power supply voltage VR for operating a system including an IC7, i.e. an one-chip MPU3 normally when the electronic instrument 2 including the one-chip MPU3 is turned to the operating state and the power supply voltage VA is changed from a prescribed value 5V to recessed state because of the instantaneous disconnection of the power supply on the way, an NMI terminal is turned to 'L' and an interruption processing routine is started to execute processing for receding necessary information into the RAM. When the power supply voltage VA is boosted again more than the power supply voltage VR without being dropped less than a lower threshold voltage V1, the output of the IC7 is turned to 'H' and the interruption mode is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application] The present invention relates to a backup reset circuit suitable for electronic equipment using a one-chip microcomputer equipped with a RAM and a ROM.

[Background Art] In recent years, various electronic devices have been equipped with microcomputers to improve their functions, make them easier to operate, and ensure safety.

Microcomputers installed in the various electronic devices mentioned above require only a narrow degree of freedom, and in order to mass produce or reduce costs, ROM, R
One-chip microcomputers with integrated AM are widely used.

By the way, when using the above-mentioned microcomputer or one-chip microcomputer, the initial states of memory, registers, etc. are random when the N source is turned on, etc.
A reset circuit is required to set these to predetermined initial state values and monitor the operation.

For this reason, it is conceivable to form a reset circuit by providing, for example, means for detecting whether the power supply voltage has reached the operating voltage of the microcomputer, and generating a signal for performing a reset operation using the output of this detecting means. However, in this reset circuit, the reset operation becomes unstable when the power supply is interrupted.

For this reason, for example, in the conventional example disclosed in Japanese Unexamined Patent Publication No. 37610, the voltage required for the reset operation is applied to the microcomputer when the power is turned on, and the microcomputer operates reliably without malfunctioning even when the power is interrupted. I'm trying to make it possible.

[Problems to be Solved by the Invention] However, the above-mentioned conventional example cannot be applied to a one-chip microcomputer equipped with RAM and ROM, since the signals required for initialization etc. are different.

In addition, recently, by installing a RAM using C-MOS, even when the power is turned off, the internal RAM memory contents are backed up by a backup power supply and parameter settings etc. can be re-set from the initial state. There are some electronic devices that are easier to use by making it possible to continue the process without having to worry about it, but the above conventional example cannot deal with this problem.

The present invention has been made in view of the above-mentioned points, and is not only able to cope with turning on the power supply voltage, but also allows RAM1. :An object of the present invention is to provide a backup reset circuit that can hold saved memory contents and perform memory backup.

[Means and effects for solving the problem] The present invention includes a voltage monitoring means that detects a power supply voltage necessary for system operation and generates an interrupt signal when the power supply voltage becomes lower than the power supply voltage;
The power supply is turned off by providing a voltage monitoring means that detects that the voltage has become higher than the power supply voltage, outputs the output with a delay, and does not activate the reset until the voltage drops to lower than the power supply voltage. In this case, memory backup is performed and a predetermined reset operation is performed when the power is turned on.

[Example] Hereinafter, the present invention will be specifically described with reference to the drawings.

1 to 3 relate to one embodiment of the present invention, FIG. 1 shows the configuration of the main part of the embodiment, and FIG. 2 shows the timing of signals necessary for memory backup and reset operation. FIG. 3 does not show a timing chart for explaining the operation of one embodiment.

As shown in FIG. 1, in an electronic device 2 equipped with a backup reset circuit 1 according to one embodiment, an 8-bit HD6301V, for example, is used as a 1-chip microcomputer (hereinafter referred to as 1-chip MPU) 3. This HD
The 6301V is equipped with a ROM 4 for programs written in accordance with the electronic device 2 and a RAM 5 as a memory for program execution or a memory for saving register information. By the way, the above-mentioned 1-chip MPU3 has an internal RAM
In order to back up 5 and execute the reset operation, (1) When the power is turned on, the NMI
(non-maskable interconnected) terminal and 5TBY (
After the signal level applied to both terminals of the standby bit (standby bit) terminal becomes high level (H”), the 1-chip MPU
As the excavation startup time T1 until normal oscillation of the internal clock of 3, for example, it is necessary to set RES (reset > m child (level) to "H11" after a time of 2Qm[5ec1 or more. 2) When the power is off, the MMI (as shown in Figure 2)
Time T2 required for the terminal to go to low level (“L”) and to perform backup preprocessing to save necessary information to internal RAM 5 in the interrupt routine by NMl
After 5TBY, it is necessary for the RES terminal to become "L". In this case, after time T2, 5 TBY,
Either RES may become "L" first.

A reset circuit 1 that satisfies the above (1) and (2) is constructed as shown in FIG.

The detection voltage can be set externally using components, and the hysteresis width of the detection voltage can be set externally.
For voltage monitoring) IC6 (for example, TL7700), a resistor R1 is connected between the power supply terminal VCC to which the power supply voltage VA is applied and the detection voltage setting terminal VR, and a resistor R2 is connected between this setting terminal Vs and the GND terminal. And a terminal CT for setting the extension time.
A capacitor C1 is connected between the and GND terminals, and this (C
The output terminal R of 6 is connected to the RES terminal of the 1-chip MPU 3.

The voltage detection IC 6 as the first voltage monitoring means includes:
The lower threshold voltage v1 is determined by the resistors R and R2.
(for example, 3.08 V) is lower than the power supply voltage VR (for example, 4.2 V) at which the output of the voltage detection 107 outputs a high-level signal, and is a higher threshold voltage with hysteresis ■2 (For example, V1+1.55
=4.63V) is set higher than the above power supply voltage VR (lower than the predetermined power supply voltage (5■)).

By selecting the value of the capacitor C1 after the voltage detection IC 6 is powered on, the voltage detection IC 6 can be configured to move from ``V'' to ``V'' after its output exceeds the higher threshold voltage 2. 41: is set so that the time 11 (for example, 37.6 m5ec) until inversion to 'H' is longer than the time T1 required for normal oscillation of the internal clock.

In other words, set tl>T1. However, the above IC
6 is designed to maintain H'' until the power supply voltage VA reaches (reduces) the lower threshold voltage V1 when the power is turned off.

On the other hand, the reset signal generating IC (for example, PST518B) 7 used as the second voltage monitoring means has the power supply voltage V^ applied to its power supply terminal Vcc, and its output terminal OU
T is connected to the NMI terminal of the one-chip MPtJ3, and when the voltage level of the power supply terminal Vcc reaches a predetermined voltage VR necessary to allow the system to operate without any trouble, the output terminal 0LJT goes high.

If the level is below VR, the output becomes low level and an (unmasked) interrupt is generated.

By the way, in order to reduce power consumption, the 1-chip MPU 3 is provided with a 5TBY terminal that controls the 1-chip MPU 3 to operate only when necessary (if this terminal is "L II", the internal RAM 5 (This is so that the outputs of both ICs 6 and 7 are applied to the 5TBY terminal via the OR circuit 8.) However, when the power is turned on, the output of IC7 causes the RES terminal to go to H' at the same time as l'JMI and after t1 time.
”), while when the power is turned off, IC6
After NMI is set to "L'' by the output of
A is held at "H" until it reaches the lower threshold voltage V1. In this case, for example, by setting the maximum capacity of a smoothing capacitor in a power supply circuit (not shown) to a large value, the above-mentioned electric power! The time required for the voltage to drop from VR to ■1 is set to 12 or more so that the backup processing routine to the RAM 5 can be completed.

In addition, the power supply voltage ＾ is applied to the power supply end VC of one chip MPtJ3 via the forward diode D1, and if the power supply voltage VA falls below a predetermined level and the system cannot operate, the power supply voltage information, that is, R
In order to retain only the memory contents saved to AM5, the backup type ME1 has forward diodes D2 and C.
3 so that it can be applied to the power supply terminal Vc. In this case, the voltage VE of the backup power supply E1 is such that the power supply voltage VA is slightly lower than this voltage vE, and the diode D
, C3 is turned on and Dl is turned off, it is applied to the power supply terminal Vc. Note that capacitors c2 and C3 are connected between the power supply end Vcc and the GND terminal of IC6 and IC7, respectively, to reduce the sensitivity of both voltage monitoring (voltage detection) ICs, and to increase the resistance to line noise by 1: It's spreading.

The operation of one embodiment constructed in this way will be explained below with reference to FIG.

First, the power is turned on and the power supply voltage VA is as shown in FIG. 3(a).
It rises in a slope as shown in the figure. When this power supply voltage VA exceeds the lower threshold voltage V, is larger than this threshold voltage 1, and exceeds the signal generation start voltage VR of 107, as shown in FIG. 3(b), This lc7
The output VB becomes "H", the NMI terminal becomes "H", and the output vS to the 5TBY terminal shown in Fig. 3(c)
□6. becomes “°H”.

Therefore, the time t (>
After T1), the output of IC6 becomes "H", and therefore the voltage to the RES terminal becomes 6, as shown in FIG. 3(d).
3 becomes “H”. In this case, since the time from when the NM1.5TBY terminal goes "H" until the RES terminal goes "H" is longer than the time T1 for the internal clock to operate stably, the 1-chip MPU3 is not reset. to ensure that the predetermined initial state is set. Furthermore, NMI, 5 TBY
, RES become active at "Shi", respectively.

Further, when the electronic device 2 equipped with the one-chip MPU 3 enters the operating state, for example, the power is momentarily cut off midway through, and as a result, the electric VA voltage V
If A changes in voltage from the predetermined value of 5■ in a concave shape,
The voltage level when it drops is IC7 or 1 chip MP.
When the power supply voltage VR becomes lower than that which allows the system including U3 to operate normally, the NMI terminal is set to L'', an interrupt handling routine is activated, and necessary information is saved in the RAM 5. When the power supply voltage VA does not go below the lower threshold voltage ■1 and rises again to exceed the power supply voltage VR, the output of IC7 becomes "H",
Interrupt mode is stopped. In this case, the information saved in the RAM 5 in interrupt mode can be used to return to the state interrupted by the voltage change and continue by activating the interrupt return program without operating reset 1- again. You can perform the operation using

If you turn off the power after using electronic device 2 above (
(or in the case of a power outage), if the power supply voltage VA falls below VR, I
The output of C7 causes the NMI terminal to go low and the interrupt handling routine is activated.

Therefore, after being set to "L II", the processing threshold voltage of this routine reaches ■1.
6, the 5TBY and RES terminals are set to “L II
be made into Also, immediately or just before this, the backup power
E1 will be applied to the power source Vo of the one-chip MPLJ3, and the memory contents of the RAM 5 will be backed up.

In addition, the voltage of the power supply terminal VC of one chip MPtJ3 (this is also V
C) indicates that, as shown in FIG. 3(e), when the power supply voltage VA is lower than approximately the backup voltage (2), backup will be performed by the backup power supply E1.

In the first embodiment, a delay output means is interposed on the output side of the IC6, while the IC6 simply has a hysteresis characteristic (when the detected power supply voltage exceeds the higher threshold voltage ■2, the output is " It is also possible to use a voltage detection means (which can be formed by a comparator or the like) having a voltage detection means (which can be formed by a comparator or the like).

In the first embodiment, the electronic device 2 is, for example, a cauterization power source, and the one-chip MPU 3 is used for controlling it. However, the power was turned on.

When it is off, the state of the 1-chip MPU3 boat may become unstable, so the display LED on the panel may flash or a warning buzzer may sound. To prevent this, , the output of tC7 is connected to a panel lighting control IC (for example, 74LS) via a diode (not shown).
138 (ENABL terminal) to prevent blinking, and the output of IC6 is applied to the buzzer drive circuit to suppress the generation of unnecessary buzzer sounds.

According to one embodiment that operates in this way, it is possible to retain necessary information in the RAM even if the power supply voltage fluctuates or is turned on or off, and it is also possible to perform a predetermined reset operation when necessary.

Therefore, the reliability of electronic equipment can be improved and the operability can be improved.

Note that the present invention is not limited to the above-mentioned one-chip MPU, but is applicable to other Motorola-based one-chip MPUs.
It can be applied when using U, and it can also be applied when using 8048.8049.8050 from Intel, NEC, etc. Also, it can be applied when using 1 chip M without 5TBY terminal.
The present invention is also applicable to PU.

Furthermore, not only 1-chip MPU but also external ROM, RA
A similar operation can be performed even in the case of a microcomputer equipped with M. For example, when the power is turned off, necessary information may be saved in RAM by interrupt processing, and the RAM may be backed up by a backup power source, so that substantially the same operation as in the above embodiment can be performed. [Effect] As described above, according to the present invention, a voltage monitoring means having a hysteresis characteristic is provided, and its output is applied to the reset terminal of the microcomplexer, and the voltage between the hysteresis voltages to be monitored is A voltage monitoring means is provided and its output is applied to the interrupt terminal so that if the power supply fluctuates, the necessary information can be saved to RAM and backed up.This ensures a reset operation when the power is turned on. Or you can let it happen and turn it off. The contents of the RAM can be retained even if the power supply voltage fluctuates between It.

[Brief explanation of drawings]

1 to 3 relate to one embodiment, FIG. 1 is a circuit diagram showing the configuration of one embodiment, and FIG. 2 is a circuit diagram showing the configuration of one embodiment. Timing chart diagram showing timing, 3rd
The figure is a timing chart diagram for explaining the operation of one embodiment.

Claims (1)

[Claims] In an electronic device equipped with a microcomputer capable of retaining the contents of a predetermined memory using a backup power supply when the power supply voltage is lower than a predetermined level, the first power supply voltage monitoring means has a hysteresis characteristic; and a second power supply voltage monitoring means for detecting a power supply voltage necessary for system operation between the detection voltages of the first monitoring means and outputting a signal, and delaying the output of the first monitoring means. By applying the voltage to the reset terminal of the microcomputer through the means and applying the output of the second monitoring means to the interrupt terminal of the microcomputer, information can be stored in the memory as appropriate in response to changes in the power supply voltage such as when the power is turned off or turned on. 1. A backup reset circuit, characterized in that the memory is evacuated to the memory, and the memory can be backed up and reset by a backup power source.